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6.5.5
DSP Status Register (DSR)
23
22
21
20
19
18
HACT
Reserved, read as zero
Bit
0
1
2
3-5
23
22-6
The DSR is a 24-bit read-only status register used by the DSP56300 core to examine the
status and flags of the HI32. The DSR cannot be accessed by the host processor. The DSR
bits are described in the following paragraphs.
6.5.5.1
Host Command Pending (HCP) Bit 0
The HCP bit indicates that the host has set the HC bit and that a host command interrupt
is pending. The HCP bit reflects the status of the HC bit in the HCVR. If HCP is set and
HCIE is set, a host command interrupt request is generated. HC and HCP are cleared by
the HI32 interrupt logic hardware when the HC interrupt request is serviced. The host
cannot clear HC.
The personal software reset clears HCP.
6.5.5.2
Slave Transmit Data Request (STRQ) Bit 1
The STRQ bit indicates that the slave transmit data FIFO (DTXS) is not full and may be
written by the DSP56300 core. STRQ functions in accordance with the value of the slave
fetch type (SFT) bit in the host control register (HCTR).
In the Fetch mode: the HI32 requests data from the DSP56300 core (by enabling the
STRQ status bit and generating core interrupt requests or DMA requests if enabled),
only after the host has begun a read transaction from the HI32.
In the Pre-Fetch mode: the HI32 requests data from the DSP56300 core (by enabling the
STRQ status bit and generating core interrupt requests or DMA requests if enabled)
whenever the DTXS is not full.
MOTOROLA
17
16
15
14
13
12
Name
HCP
Host Command Pending
STRQ
Slave Transmit Data Request
SRRQ
Slave Receive Data Request
HF2-HF0
Host Flags
HACT
HI32 Active
reserved
DSP56305 User's Manual
DSP SIDE Programming Model
11
10
9
8
7
6
Function
HOST INTERFACE (HI32)
5
4
3
2
1
HF2 HF1 HF0 SRRQ STRQ HCP
6-35
0
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