Table 14-6 Ccop Interrupt Vectors; Parity Coding Done Bit (Pcdn)—Ccsr Bit 23; Cyclic Code Processing Registers - Motorola DSP56305 User Manual

data words previously generated and transferred to the output FIFO. CIDN can also be
cleared by reading CFSRA- this is used when CCOP processing is terminated without
entering the output phase (e.g. Output Counter = 0). CIDN is cleared by hardware,
software, or CCOP individual reset.
14.4.4.15 Parity Coding Done bit (PCDN)—CCSR Bit 23
The read-only status bit Parity Coding Done (PCDN), when set, indicates that Parity
Coding processing on the input data block is terminated. PCDN is enabled when CCOP
operates in the Parity Coding modes (OPM1 = 1) and is disabled otherwise. PCDN is set
when the CCOP has completed all phases of the processing (i.e., the Input and Run
phases). If HOZD is set, Parity Coding processing terminates either when the Run
Counter reaches zero or when a zero was detected by the Zero Detect function, and then
PREN is cleared and PCDN is set. These conditions allow easy implementation of cyclic
Fire decoders for burst error detection and correction. As a result, the contents of the
Run Counter can be used to calculate the location of the erroneous burst in the data
block, and the contents of CFSRs (CFSRA and CFSRB) can be used to determine the burst
correction sequence. If PCDN and PDIE are set, a Parity Coding Done interrupt vector is
generated. PCDN is cleared when CFSRA is read by the DSP56300 core. PCDN is cleared
by hardware, software. or CCOP individual reset.
Interrupt options are summarized in Table .
Interrupt
Address
VBA+Base+0
VBA+Base+2
VBA+Base+4
VBA+Base+6 Parity Coding Processing Done
14.4.5

Cyclic Code Processing Registers

These registers are grouped into four identical sets, so this discussion refers to them
generically (for instance as CFSR) instead of individually (for instance as CFSRA,
CFSRB, CFSRC, or CFSRD). In programming these registers, it is necessary to specify
which of the register sets are being programmed (A, B, C, or D).
MOTOROLA

Table 14-6 CCOP Interrupt Vectors

Interrupt
Vector
Input FIFO Empty
Output FIFO Not Empty
Cipher Processing Done
DSP56305 User's Manual
CYCLIC CODE CO-PROCESSOR
CCOP Programming Model
Interrupt Interrupt
Enable Conditions
DIIE INFE = 1
DOIE OFNE = 1
CDIE CIDN = 1
PDIE PCDN = 1
DMA
Capability
Yes
No
Yes
No
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