Motorola DSP56305 User Manual page 651

A
adder
modulo 1-9
offset 1-9
reverse-carry 1-9
Address Generation Unit 1-9
Address Tracing Enable bit (ATE) 4-22
addressing modes 1-10
AGU 1-9
ALC bit 7-18
Alignment Control bit (ALC) 7-18
Asynchronous/Synchronous bit (SYN) 7-24
ATE 4-22
ATE bit 4-22
B
barrel shifter 1-8
bootstrap 4-5
bootstrap from byte-wide external memory 4-8
bootstrap program options
invoking 4-5
bootstrap ROM 3-4
bootstrap through SCI 4-8
Boundary Scan Register (BSR) 11-7
break 8-10
Breakpoint 0 and 1 Event bits (BT0–BT1) 10-14
Breakpoint 0 Condition Code Select bits
(CC00–CC01) 10-13
Breakpoint 0 Read/Write Select bits
(RW00–RW01) 10-12
Breakpoint 1 Condition Code Select bits
(CC10–CC11) 10-14
Breakpoint 1 Read/Write Select bits
(RW10–RW11) 10-13
BSR register 11-7
BT0–BT1 bits 10-14
bus
external address 2-9
external data 2-9
buses
internal 1-13
BYPASS instruction 11-12
C
CC00–CC01 bits 10-13
CC10–CC11 bits 10-14
CD0–CD11 bits 8-18
Central Processing Unit (CPU) 1-3
MOTOROLA
INDEX
CKP bit 7-24
CLAMP instruction 11-10
CLKGEN 1-11
Clock 2-8
clock 1-7
Clock Divider bits (CD0–CD11) 8-18
Clock Generator (CLKGEN) 1-11
Clock Out Divider bit (COD) 8-18
Clock Polarity bit (CKP) 7-24
Clock Source Direction bit (SCKD) 7-22
CMOS 1-7
COD bit 8-18
code
Core Status bits (OS0–OS1) 10-9
CRA register 7-15
CRB register
DSP56305 User's Manual
compatible 1-7
bits 0–7—Prescale Modulus Select bits
(PM0–PM7) 7-15
bits 8–10—reserved bits 7-15
bit 11—Prescaler Range bit (PSR) 7-15
bit 17—reserved bit 7-18
bit 18—Alignment Control bit (ALC) 7-18
bits 19–21—Word Length Control bits
(WL0–WL1) 7-19
bit 22—Select SC1 as Transmitter 0 Drive
Enable bit (SSC1) 7-19
bit 23—reserved bit 7-19
reserved bits—bit 17 7-18
reserved bits—bit 23 7-19
reserved bits—bits 8–10 7-15
bits 0–1—Serial Output Flag bits
(OF0–OF1) 7-20
bit 2—Serial Control 0 Direction bit
(SCD0) 7-21
bit 3—Serial Control 1 Direction bit
(SCD1) 7-22
bit 4—Serial Control 2 Direction bit
(SCD2) 7-22
bit 5—Clock Source Direction bit (SCKD) 7-22
bit 6—Shift Direction bit (SHFD) 7-22
bits 7–8—Frame Sync Length bits
(FSL1–FSL0) 7-22
bit 9—Frame Sync Relative Timing bit
(FSR) 7-23
bit 10—Frame Sync Polarity bit (FSP) 7-23
bit 11—Clock Polarity bit (CKP) 7-24
bit 12—Asynchronous/Synchronous bit
(SYN) 7-24
bit 13—ESSI Mode Select bit (MOD) 7-27
bit 14—ESSI Transmit 2 Enable bit (TE2) 7-29
Index-1