Motorola DSP56305 User Manual page 516

VITERBI CO-PROCESSOR
Programming Examples
movep #$0000,y:M_VBER
nop
nop
movep y:M_VMEM,y:(r4)
movep y:M_VMEM,y:(r4)
rep #8
movep y:M_VMEM,y:(r4)+
;************************************
; Example of memory access to read the SP memory in VCOP (not necessary)
;************************************
movep #$0040,y:M_VBER
nop
nop
movep y:M_VMEM,y:(r4)
movep y:M_VMEM,y:(r4)
rep #7
movep y:M_VMEM,y:(r4)+
;************************************
; Process First Half of Normal Burst
;************************************
; Initialize input DMA channel
movep #$150,x:M_DSR0
movep #M_VDR,x:M_DDR0
movep #60,x:M_DCO0
movep #$8CAA54,x:M_DCR0 ; word transfers
; Initialize output DMA channel
movep #M_VDOR,x:M_DSR1
movep #$0,x:M_DDR1
movep #60,x:M_DCO1
movep #$86C2C1,x:M_DCR1 ; block transfer
movep #60,y:M_VCNT
movep #$0401,y:M_VTSR
movep #$1011,y:M_VCRA
jclr #4,y:M_VSTR,*
nop
nop
;************************************
; Process Second Half of Normal Burst
;************************************
; Initialize input DMA channel
movep #$200,x:M_DSR0
movep #M_VDR,x:M_DDR0
movep #60,x:M_DCO0
13-46
; pipeline delay
; pipeline delay
; dummy read
; dummy read
; pipeline delay
; pipeline delay
; dummy read
; dummy read
; source address
; destination address
; 61 bits (61 transfers)
; source address
; destination address
; 61 bits (61 transfers)
; 61 bits (half of Normal Burst)
; ES=4,IS=1
; enable Equalization mode
; wait till OPC
; source address
; destination address
; 61 bits (61 transfers)
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