ST STM32L4+ Series Reference Manual page 2026

Secure digital input/output MultiMediaCard interface (SDMMC)
Bits 7:4 DBLOCKSIZE[3:0]: Data block size
Bits 3:2 DTMODE[1:0]: Data transfer mode selection
Bit 1 DTDIR: Data transfer direction selection
Bit 0 DTEN: Data transfer enable bit
54.9.10 SDMMC data counter register (SDMMC_DCNTR)
Address offset: 0x030
Reset value: 0x0000 0000
The SDMMC_DCNTR register loads the value from the data length register (see
SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state.
As data is transferred, the counter decrements the value until it reaches 0. The DPSM then
2026/2301
This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
Define the data block length when the block data transfer mode is selected:
0000: (0 decimal) lock length = 2
0001: (1 decimal) lock length = 2
0010: (2 decimal) lock length = 2
0011: (3 decimal) lock length = 2
0100: (4 decimal) lock length = 2
0101: (5 decimal) lock length = 2
0110: (6 decimal) lock length = 2
0111: (7 decimal) lock length = 2
1000: (8 decimal) lock length = 2
1001: (9 decimal) lock length = 2
1010: (10 decimal) lock length = 2
1011: (11 decimal) lock length = 2
1100: (12 decimal) lock length = 2
1101: (13 decimal) lock length = 2
1110: (14 decimal) lock length = 2
1111: (15 decimal) reserved
When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a
multiple of DBLOCKSIZE. (Any remain data will not be transfered.)
When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)
This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
00: Block data transfer ending on block count.
01: SDIO multibyte data transfer.
10: e•MMC Stream data transfer. (WIDBUS shall select 1-bit wide bus mode)
11: Block data transfer ending with STOP_TRANSMISSION command (not to be used with
DTEN initiated data transfers).
This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
0: From host to card.
1: From card to host.
This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is
cleared by Hardware when data transfer completes.
This bit shall only be used to transfer data when no associated data transfer command is
used, i.e. shall not be used with SD or e•MMC cards.
0: Do not start data transfer without CPSM data transfer command.
1: Start data transfer without CPSM data transfer command.
0
= 1 byte
1
= 2 bytes
2
= 4 bytes
3
= 8 bytes
4
= 16 bytes
5
= 32 bytes
6
= 64 bytes
7
= 128 bytes
8
= 256 bytes
9
= 512 bytes
10
= 1024 bytes
11
= 2048 bytes
12
= 4096 bytes
13
= 8192 bytes
14
= 16384 bytes
RM0432 Rev 6
RM0432