ST STM32L4+ Series Reference Manual page 1965

RM0432
54.4 SDMMC operation modes
SDIO Bus Speed modes
DS (Default Speed)
HS (High Speed)
SDR12
SDR25
DDR50
SDR50
1. SDR single data rate signaling.
2. DDR double data rate signaling. (data is sampled on both SDMMC_CK clock edges).
3. SDIO bus speed with 4bit bus width.
4. Maximum frequency depending on maximum allowed IO speed.
e•MMC bus speed modes
Legacy compatible
High speed SDR
High speed DDR
1. SDR single data rate signaling.
2. DDR double data rate signaling. (data is sampled on both SDMMC_CK clock edges).
3. e•MMC bus speed with 8bit bus width.
4. Maximum frequency depending on maximum allowed IO speed.
54.5 SDMMC functional description
The SDMMC consists of three parts:
•
The AHB slave interface accesses the SDMMC adapter registers, and generates
interrupt signals and IDMA control signals.
•
The SDMMC adapter block provides all functions specific to the e•MMC/SD/SD I/O
card such as the clock generation unit, command and data transfer.
• The internal DMA (IDMA) block with its AHB master interface.
Secure digital input/output MultiMediaCard interface (SDMMC)
Table 383. SDMMC operation modes SD & SDIO
Max Bus Speed
(1)(2)
[MByte/s]
12.5
25
12.5
25
50
50
Table 384. SDMMC operation modes e•MMC
Max bus speed
(1)(2)
[MByte/s]
26
52
104
RM0432 Rev 6
(3)
Max Clock frequency
(4)
[MHz]
25
50
25
50
50
100
(3)
Max clock frequency
(4)
[MHz]
26
52
52
Signal Voltage
[V]
3.3
3.3
1.8
1.8
1.8
1.8
Signal voltage
[V]
3/1.8/1.2V
3/1.8/1.2V
3/1.8/1.2V
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