ST STM32L4+ Series Reference Manual page 2000

Secure digital input/output MultiMediaCard interface (SDMMC)
In ReadWait SDMMC_CK clock stopping, when RWSTART is set, the DSPM stops the clock
after the End bit of the current received data block CRC. The clock start again after writing 1
to the RWSTOP bit, where after the DPSM waits for a Start bit from the card.
As SDMMC_CK is stopped, no command can be issued to the card. During a ReadWait
interval, the SDMMC can still detect SDIO interrupts on SDMMC_D1.
The optional ReadWait signaling on SDMMC_D2 (RW) operation is defined only for the SD
1-bit and 4-bit modes. The ReadWait operation allows the host to signal a card that is
reading multiple registers (IO_RW_EXTENDED, CMD53) to temporarily stall the data
transfer while allowing the host to send commands to any function within the SD I/O device.
To determine when a card supports the ReadWait protocol, the host must test capability bits
in the internal card registers.
The timing for ReadWait with a SDMMC_CK less then 50MHz (DS, HS, SDR12, SDR25) is
based on the interrupt period generated by the card on SDMMC_D1. The host by asserting
SDMMC_D2 low during the interrupt period requests the card to enter ReadWait. To exit
ReadWait the host shall raise SDMMC_D2 high during one SDMMC_CK cycles before
making it Hi-Z, see
SDMMC_CK
SDMMC_D1
SDMMC_D2
SDMMC_D3
SDMMC_D0
SDMMC_CMD
For SDR50 with a SDMMC_CK more than 50MHz, and DDR50, the card will treat the
ReadWait request on SDMMC_D2 as an asynchronous event. The host by asserting
SDMMC_D2 low after minimum 2 SDMMC_CK cycles and maximum 5 SDMMC_CK cycles,
request the card to enter ReadWait. To exit ReadWait the host shall raise SDMMC_D2 high
during one SDMMC_CK cycles before making it Hi-Z. The host shall raise SDMMC_D2 on
the SDMMC_CK clock (see
2000/2301
Figure 590.
Figure 590. ReadWait with SDMMC_CK < 50 MHz
2 CK 2 CK
Read data
Read data
Read data Int period
Figure 591).
RM0432 Rev 6
Read wait
CMD
RM0432
Read data
2 CK
Read data
Read data
MSv40941V2