ST STM32L4+ Series Reference Manual page 1972

Secure digital input/output MultiMediaCard interface (SDMMC)
–
• Wait: The Command path waits for a response.
–
a)
b)
–
a)
b)
•
Receive: The command response will be received. Depending the response mode bits
WAITRESP in the command control register, the response can be either short or long,
with CRC or without CRC. The received CRC code when present will be verified
against the internally generated CRC code.
–
–
–
–
•
Pending: According the pending WAITPEND bit in the command register, the CPSM
enters the pending state.
–
–
1972/2301
CMDSENT flag is generated immediately after the command End bit.
The RESPCMDR and RESPxR registers are not modified.
If a command response is expected (WAITRESP = not 00) the CPSM will move to
the Wait state and start the response timeout.
When WAITINT bit is 0 the command timer starts running and the CPSM waits for
a Start bit.
If a Start bit is detected before the timeout the CPSM moves to the Receive state.
If the timeout is reached before the CPSM detect a response start bit, the timeout
flag (CTIMEOUT) is set and the CPSM moves to the Idle state.
The RESPCMDR and RESPxR registers are not modified.
When WAITINT bit is 1, the timer is disabled and the CPSM waits for an interrupt
request (Response Start bit) from one of the cards.
When a Start bit is detected the CPSM moves to the Receive state.
When writing WAITINT to 0 (interrupt mode abort), the host will send a response
by its self and on detecting the Start bit the CPSM move to the Receive state.
When the CMDSUSPEND bit is set and the SDIO Response bit BS = 0 (response
bit [39]), the interrupt period will be started after the response.
When the CMDSUSPEND bit is cleared, or the CMDSUSPEND bit is 1 and the
SDIO Response bit BS = 1 (response bit [39]), there will be no interrupt period
started.
When the CMDTRANS bit is set and the CMDSUSPEND bit is set and the SDIO
Response bit DF= 1 (response bit [32]) the interrupt period will be terminated after
the response.
When the CRC status passes or no CRC is present the CMDREND flag is set, the
CPSM moves to the Idle state.
The RESPCMDR and RESPxR registers are updated with received response.
- When BOOTMODE = 1 & BOOTEN = 0 the CMDREND flag is delayed 56 cycles
after the response End bit, otherwise the CMDREND flag is generated
immediately after the response End bit.
- When CMDTRANS bit is set and the DTDIR = transmit, the CPSM DataEnable
signal will be issued to the DPSM at the end of the command response.
When the CRC status fails the CCRCFAIL flag is set and the CPSM moves to the
Idle state.
The RESPCMDR and RESPxR registers are updated with received response.
When DATALENGTH =< 5 bytes the CPSM moves to the Sent state and
generates the DataEnable signal to start the data transfer aligned with the CMD12
Stop Transmission command.
When DATALENGTH > 5 bytes, the CPSM DataEnable signal will be issued to the
DPSM to start the data transfer. The CPSM waits for a sendCMD signal from the
RM0432 Rev 6
RM0432