ST STM32L4+ Series Reference Manual page 2035

RM0432
54.9.14 SDMMC acknowledgment timer register (SDMMC_ACKTIMER)
Address offset: 0x040
Reset value: 0x0000 0000
The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in
SDMMC_CK bus clock periods.
A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing
when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0
while the DPSM is in this states, the acknowledgment timeout status flag is set.
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
rw rw rw rw
Bits 31:25 Reserved, must be kept at reset value.
Bits 24:0 ACKTIME[24:0]: Boot acknowledgment timeout period
Note: The data transfer must be written to the acknowledgment timer register before being written
to the data control register.
54.9.15 SDMMC data FIFO registers x (SDMMC_FIFORx)
Address offset: 0x080 + 0x004 * x, (x =0 to 15)
Reset value: 0x0000 0000
The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers.
The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load
and store multiple operands to read from/write to the FIFO. The FIFO register interface
takes care of correct data alignment inside the FIFO, the FIFO register address used by the
CPU does matter.
When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is
generated.
31 30 29 28
rw rw rw rw
15 14 13 12
rw rw rw rw
Secure digital input/output MultiMediaCard interface (SDMMC)
27 26 25
Res. Res. Res.
11 10 9
rw rw rw
This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0).
Boot acknowledgment timeout period expressed in card bus clock periods.
27 26 25
rw rw rw
11 10 9
rw rw rw
24 23 22
rw rw rw
8 7 6
ACKTIME[15:0]
rw rw rw
24 23 22
FIFODATA[31:16]
rw rw rw
8 7 6
FIFODATA[15:0]
rw rw rw
RM0432 Rev 6
21 20 19 18
ACKTIME[24:16]
rw rw rw rw
5 4 3 2
rw rw rw rw
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
17 16
rw rw
1 0
rw rw
17 16
rw rw
1 0
rw rw
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