ST STM32L4+ Series Reference Manual page 2017

RM0432
54.9 SDMMC registers
The device communicates to the system via 32-bit control registers accessible via AHB
slave interface.
The peripheral registers have to be accessed by words (32-bit). Byte (8-bit) and halfword
(16-bit) accesses trigger an AHB bus error.
54.9.1 SDMMC power control register (SDMMC_POWER)
Address offset: 0x000
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:5 Reserved, must be kept at reset value.
Bit 4 DIRPOL: Data and command direction signals polarity selection
Bit 3 VSWITCHEN: Voltage switch procedure enable
Bit 2 VSWITCH: Voltage switch sequence start
Bits 1:0 PWRCTRL[1:0]: SDMMC state control bits
Secure digital input/output MultiMediaCard interface (SDMMC)
27 26 25
Res. Res. Res.
11 10 9
Res. Res. Res.
This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00).
0: Voltage transceiver IOs driven as output when direction signal is low.
1: Voltage transceiver IOs driven as output when direction signal is high.
This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0).
This bit is used to stop the SDMMC_CK after the voltage switch command response:
0: SDMMC_CK clock kept unchanged after successfully received command response.
1: SDMMC_CK clock stopped after successfully received command response.
This bit is used to start the timing critical section of the voltage switch sequence:
0: Voltage switch sequence not started and not active.
1: Voltage switch sequence started or active.
These bits can only be written when the SDMMC is not in the power-on state
(PWRCTRL ≠ 11).
These bits are used to define the functional state of the SDMMC signals:
00: After reset, Reset: the SDMMC is disabled and the clock to the Card is stopped,
SDMMC_D[7:0], and SDMMC_CMD are HiZ and SDMMC_CK is driven low.
When written 00, power-off: the SDMMC is disabled and the clock to the card is
stopped, SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are driven high.
01: Reserved. (When written 01, PWRCTRL value will not change)
10: Power-cycle, the SDMMC is disabled and the clock to the card is stopped,
SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are driven low.
11: Power-on: the card is clocked, The first 74 SDMMC_CK cycles the SDMMC is still
disabled. After the 74 cycles the SDMMC is enabled and the SDMMC_D[7:0],
SDMMC_CMD and SDMMC_CK are controlled according the SDMMC operation.
Any further write will be ignored, PWRCTRL value will keep 11.
24 23 22
Res. Res. Res. Res.
8 7 6
Res. Res. Res. Res.
RM0432 Rev 6
21 20 19 18
Res. Res. Res.
5 4 3 2
DIR VSWI VSWI
POL TCHEN TCH
rw rw rw
17 16
Res. Res.
1 0
PWRCTRL[1:0]
rw rw
2017/2301
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