ST STM32L4+ Series Reference Manual page 1978

Secure digital input/output MultiMediaCard interface (SDMMC)
In DDR mode, data is sampled on both edges of the SDMMC_CK according the following
rules, see also
•
On the rising edge of the clock Odd bytes are sampled.
•
On the falling edge of the clock Even bytes are sampled.
•
Data payload size is always a multiple of 2 Bytes.
•
Two CRC16 are computed per data line
–
–
•
Start, End bits and idle conditions are full cycle.
•
CRC status / boot acknowledgment and Busy signaling are full cycle and are only
sampled on the rising edge of the clock.
In DDR mode the SDMMC_CK clock division shall be >= 2.
SDMMC_CK
SDMMC_D3
SDMMC_D2
SDMMC_D1
SDMMC_D0
Data odd
Data even
CRC odd
CRC even
Data path state machine (DPSM)
Depending on the transfer direction (send or receive), the data path state machine (DPSM)
moves to the Wait_S or Wait_R state when it is enabled:
•
Send: the DPSM moves to the Wait_S state. If there is data in the transmit FIFO, the
DPSM moves to the Send state, and the data path subunit starts sending data to a
card.
•
Receive: the DPSM moves to the Wait_R state and waits for a start bit. When it
receives a start bit, the DPSM moves to the Receive state, and the data path subunit
starts receiving data from a card.
1978/2301
Figure 579 and
Odd bits CRC16 clocked on the falling edge of the clock.
Even bits CRC16 clocked on the rising edge of the clock.
Figure 579. DDR mode data packet clocking
Byte 2
0 b b b
7 7
start odd even odd
0 b b b
6 6
start odd even odd
0 b b b
5 5
start odd even odd
0 b b b
4 4
start odd even odd
Byte 1
Figure 580. DDR mode CRC status / boot acknowledgment clocking
SDMMC_CK
SDMMC_D0
Figure 580:
Byte 4
b b b b b b
3 3 7 7 3 3
even odd even odd even odd
b b b b b b
2 2 6 6 2 2
even odd even odd even odd
b b b b b b
1 1 5 5 1 1
even odd even odd even odd
b b b b b b
0 0 4 4 0 0
even odd even odd even odd
BYte 3
Block length
0
start
CRC status / boot ack
RM0432 Rev 6
Byte n
b b b crc crc crc crc
7 7 3 3 15 15 14 14
even odd even odd even odd even
b b b crc crc crc crc
6 6 2 2 15 15 14 14
even odd even odd even odd even
b b b crc crc crc crc
5 5 1 1 15 15 14 14
even odd even odd even odd even
b b b crc crc crc crc
4 4 0 0 15 15 14 14
even odd even odd even odd even
Byte n-1
CRC
1
end
RM0432
crc crc 1
0 0
odd even end
crc crc 1
0 0
odd even end
crc crc 1
0 0
odd even end
crc crc 1
0 0
odd even end
MSv40163V2
MSv40164V1