ST STM32L4+ Series Reference Manual page 2036

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Secure digital input/output MultiMediaCard interface (SDMMC)

Bits 31:0 FIFODATA[31:0]: Receive and transmit FIFO data

SDMMC DMA control register (SDMMC_IDMACTRLR)

Address offset: 0x050

Reset value: 0x0000 0000

The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs

contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store

multiple operands to read from/write to the FIFO.

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 IDMABACT: Double buffer mode active buffer indication

Bit 1 IDMABMODE: Buffer mode selection

Bit 0 IDMAEN: IDMA enable

This register can only be read or written by firmware when the DPSM is active

(DPSMACT = 1).

The FIFO data occupies 16 entries of 32-bit words.

This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When

IDMA is enabled this bit is toggled by hardware.

0: When IDMA is enabled, uses buffer0 and firmware write access to IDMABASE0 is

1: When IDMA is enabled, uses buffer1 and firmware write access to IDMABASE1 is

This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).

0: Single buffer mode.

1: Double buffer mode.

This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).

0: IDMA disabled

1: IDMA enabled

RM0432 Rev 6

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