ST STM32L4+ Series Reference Manual page 1973

RM0432
–
•
Boot: If the BOOTEN bit is set in the command register, the CPSM enters the boot
state, and when:
–
–
Note: The CPSM remains in the Idle state for at least eight SDMMC_CK periods to meet the N
and N
RC
N is the minimum delay between the host command and the card response.
RC
Note: The response timeout has a fixed value of 64 SDMMC_CK clock periods.
A Command is a token that starts an operation. Commands are sent from the host to either
a single card (addressed command) or all connected cards (broadcast command are
available for e•MMC V3.31 or previous). Commands are transferred serially on the
SDMMC_CMD line. All commands have a fixed length of 48 bits. The general format for a
command token for SD-Memory cards, SDIO cards, and e•MMC cards is shown in
388..
The Command token data is taken from 2 registers, one containing a 32-bits argument and
the other containing the 6-bits command index (six bits sent to a card).
Bit position
47
46
[45:40]
[39:8]
[7:1]
0
Next to the Command data there are command type (WAITRESP) bits controlling the
command path state machine (CPSM). These bits also determine whether the command
requires a response, and whether the response is short (48 bit) or long (136 bits) long, and if
a CRC is present or not.
A Response is a token that is sent from an addressed card or synchronously from all
connected cards to the host as an answer to a previous received Command. All responses
are sent via the command line SDMMC_CMD. The response transmission always starts
with the left bit of the bit string corresponding to the response code word. The code length
depends on the response type. Response tokens R1, R2, R3, R4, R5, and R6 have various
Secure digital input/output MultiMediaCard interface (SDMMC)
DPSM before moving to the Sent state. This enables i.e. the CMD12 Stop
Transmission command to be sent aligned with the data.
When writing WAITPEND to 0, the CPSM will move to the Sent state.
BOOTMODE = 0 the SDMMC_CMD line is driven low and when CMDTRANS bit
is set and the DTDIR = receive, the CPSM DataEnable signal will be issued to the
DPSM. This enables normal boot operation. This state is left at the end of the boot
procedure by clearing the register bit BOOTEN, which cause the SDMMC_CMD
line to be driven high and the CPSM Abort signal will be issued to the DPSM,
before moving to the Idle state.The CMDSENT flag is generated 56 cycles after
SDMMC_CMD line is high.
BOOTMODE = 1, move to the Send state. This enables sending of the CMD0
(boot). Clearing BOOTEN has no effect.
timing constraints. N
CC
Table 388. Command token format
Width
1
1
6
32
7
1
is the minimum delay between two host commands, and
Value
0 Start bit
1 Transmission bit
x Command index
x Argument
x CRC7
1 End bit
RM0432 Rev 6
Table
Description
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CC
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