ST STM32L4+ Series Reference Manual page 1977

RM0432
Registers
FIFO
The card data bus width can be programmed in the clock control register bits WIDBUS. The
supported data bus width modes are:
•
If the wide bus mode is not enabled, only one bit is transferred over SDMMC_D0.
•
If the 4-bit wide bus mode is enabled, data is transferred at four bits over
SDMMC_D[3:0].
•
If the 8-bit wide bus mode is enabled, data is transferred at eight bits over
SDMMC_D[7:0].
Next to the data bus width the data sampling mode can be programmed in the clock control
register bit DDR. The supported data sampling modes are:
•
Single data rate signaling (SDR), data is clocked on the rising edge of the clock.
• Double data rate signaling (DDR), data is clocked on the both edges of the clock. DDR
mode is only supported in wide bus mode (4-bit wide and 8-bit wide).
Note: The data sampling mode only applies to the SDMMC_D[7:0] lines. (not applicable to the
SDMMC_CMD line.)
Secure digital input/output MultiMediaCard interface (SDMMC)
Figure 578. Data path
Data path
Status Data
flag timer
Odd receive
shift register
Even receive
shift register
Odd transmit
shift register
Even transmit
shift register
RM0432 Rev 6
To control unit
Control
logic
Odd CRC
Even CRC
Odd CRC
Even CRC
in
SDMMC_D[7:0]
sdmmc_rx_ck
out
SDMMC_CK
MSv40162V2
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