ST STM32L4+ Series Reference Manual page 1991

RM0432
Single buffered channel
In single buffer configuration the data at the memory side is accessed in a linear matter
starting from the base address IDMABASE0. When the IDMA has finished transferring all
data the and the DPSM has completed the transfer the DATAEND flag is set.
Double buffered channel
In double buffer configuration the data at the memory side is subsequently accessed from 2
buffers, one located from base address IDMABASE0 and a second located from base
address IDMABASE1. This allows firmware to process one memory buffer while the IDMA is
accessing the other memory buffer. The size of the memory buffers is defined by
IDMABSIZE. The buffer size shall be an integer multiple of the burst size. It is possible to
update the base address of the buffers on-the-fly when the channel is enabled, the following
rule apply:
•
When IDMABACT bit is '0' the IDMA hardware uses the IDMABASE0 to access
memory. When attempting to write to this register by Firmware the write is discarded,
IDMABASE0 data will not be changed. Firmware is allowed to write IDMABASE1.
•
When IDMABACT bit is '1' the IDMA hardware uses the IDMABASE1 to access
memory. When attempting to write to this register by Firmware the write is discarded,
IDMABASE1 data will not be changed. Firmware is allowed to write IDMABASE0.
When the IDMA has finished transferring the data of one buffer the buffer transfer complete
flag (IDMABTC) is set and the IDMABACT bit toggles where after the IDMA continues
transferring data from the other buffer. When the IDMA has finished transferring all data and
the DPSM has completed the transfer the DATAEND flag is set.
The IDMABASEn address shall be word aligned.
IDMA transfer error management
An IDMA transfer error can occur:
•
When reading or writing a reserved address space.
On a IDMA transfer error subsequent IDMA transfers are disabled and an IDMATE flag is
set. Depending when the IDMA transfer error occurs, it will normally cause the generation of
a TXUNDERR or RXOVERR error.
The behavior of the IDMATE flag depend on when the IDMA transfer error occurs during the
SDMMC transfer:
•
An IDMA transfer error is detected before any SDMMC transfer error (TXUNDERR,
RXOVERR, DCRCFAIL, or DTIMEOUT):
–
–
•
An IDMA transfer error is detected during a STOP_TRANSNMISSION command:
–
–
•
An IDMA transfer error is detected at the end of the SDMMC transfer (DHOLD, or
DATAEND).
–
–
Secure digital input/output MultiMediaCard interface (SDMMC)
The IDMATE flag is set at the same time as the SDMMC transfer error flag.
The TXUNDERR, RXOVERR, DCRCFAIL, or DTIMEOUT interrupt is generated.
The IDMATE flag is set at the same time as the DABORT flag.
The DABORT interrupt is generated.
The IDMATE flag is set at the end of the SDMMC transfer.
A SDMMC transfer end interrupt is generated and a DHOLD or DATAEND flag is
set.
RM0432 Rev 6 1991/2301
2041