ST STM32L4+ Series Reference Manual page 1999

RM0432
The DPSM will either go to the Wait_S state when SDMMC_D0 does not signal busy,
or will go to the Busy state when busy is signaled.
3. When IDMAEN = 1: The IDMA needs to be reprogrammed for the remaining bytes to
be transfered.
4. When IDMAEN = 0: Firmware shall start filling the FIFO with the remaining data.
SD I/O ReadWait
There are 2 methods to pause the data transfer during the Block gap:
1. Stopping the SDMMC_CK.
2. Using ReadWait signaling on SDMMC_D2.
The SDMMC can perform a ReadWait with register settings according
Depending the SDMMC operation mode (DS, HS, SDR12, SDR25) or (SDR50, DDR) each
method has a different characteristic.
The timing for pause read operation by stopping the SDMMC_CK for DS, HS, SDR12, and
SDR25, the SDMMC_CK may be stopped 2 SDMMC_CK cycles after the End bit. When
ready the host resumes by restarting clock, see
SDMMC_CK
SDMMC_Dn
The timing for pause read operation by stopping the SDMMC_CK for SDR50 and DDR50,
the SDMMC_CK may be stopped minimum 2 SDMMC_CK cycles and maximum 5
SDMMC_CK cycles, after the End bit. When ready the host resumes by restarting clock, see
Figure 589. (In DDR50 mode the SDMMC_CK shall only be stopped after the falling edge,
when the clock line is low.)
Secure digital input/output MultiMediaCard interface (SDMMC)
Figure 588. Clock stop with SDMMC_CK for DS, HS, SDR12, SDR25
2 CK
Read data
Figure 589. Clock stop with SDMMC_CK for DDR50, SDR50
t
OP
0 1 2
SDMMC_CK
Read
1
SDMMC_Dn
data
End
2 CK min.
Figure
Interrupt period
N 8 CK min.
AC
3 4 5 6 7
5 CK max.
RM0432 Rev 6
Table
588.
1 CK 2 CK
H
t
OP
5 6 7 8 9 10
0
Start
402.
Read data
MSv40193V2
Read
data
MSv40194V2
1999/2301
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