ST STM32L4+ Series Reference Manual page 2033

RM0432
Bit 24 ACKTIMEOUTIE: Acknowledgment timeout interrupt enable
Bit 23 ACKFAILIE: Acknowledgment Fail interrupt enable
Bit 22 SDIOITIE: SDIO mode interrupt received interrupt enable
Bit 21 BUSYD0ENDIE: BUSYD0END interrupt enable
Bits 20:19 Reserved, must be kept at reset value.
Bit 18 TXFIFOEIE: Tx FIFO empty interrupt enable
Bit 17 RXFIFOFIE: Rx FIFO full interrupt enable
Bit 16 Reserved, must be kept at reset value.
Bit 15 RXFIFOHFIE: Rx FIFO half full interrupt enable
Bit 14 TXFIFOHEIE: Tx FIFO half empty interrupt enable
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 DABORTIE: Data transfer aborted interrupt enable
Bit 10 DBCKENDIE: Data block end interrupt enable
Secure digital input/output MultiMediaCard interface (SDMMC)
Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout.
0: Acknowledgment timeout interrupt disabled
1: Acknowledgment timeout interrupt enabled
Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail.
0: Acknowledgment Fail interrupt disabled
1: Acknowledgment Fail interrupt enabled
Set and cleared by software to enable/disable the interrupt generated when receiving the
SDIO mode interrupt.
0: SDIO Mode interrupt received interrupt disabled
1: SDIO Mode interrupt received interrupt enabled
Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0
signal changes from busy to NOT busy following a CMD response.
0: BUSYD0END interrupt disabled
1: BUSYD0END interrupt enabled
Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty.
0: Tx FIFO empty interrupt disabled
1: Tx FIFO empty interrupt enabled
Set and cleared by software to enable/disable interrupt caused by Rx FIFO full.
0: Rx FIFO full interrupt disabled
1: Rx FIFO full interrupt enabled
Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full.
0: Rx FIFO half full interrupt disabled
1: Rx FIFO half full interrupt enabled
Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty.
0: Tx FIFO half empty interrupt disabled
1: Tx FIFO half empty interrupt enabled
Set and cleared by software to enable/disable interrupt caused by a data transfer being
aborted.
0: Data transfer abort interrupt disabled
1: Data transfer abort interrupt enabled
Set and cleared by software to enable/disable interrupt caused by data block end.
0: Data block end interrupt disabled
1: Data block end interrupt enabled
RM0432 Rev 6 2033/2301
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