ST STM32L4+ Series Reference Manual page 1993

RM0432
ReadWait SDMMC_CK clock stop (START)
ReadWait SDMMC_CK clock stop (STOP)
ReadWait SDMMC_D2 signaling (START)
ReadWait SDMMC_D2 signaling (STOP)
SD I/O interrupts
To allow the SD I/O card to interrupt the host, an interrupt function is available on pin 8
(shared with SDMMC_D1 in 4-bit mode) on the SD interface. The use of the interrupt is
optional for each card or function within a card. The SD I/O interrupt is level-sensitive, which
means that the interrupt line must be held active (low) until it is either recognized and acted
upon by the host or deasserted due to the end of the interrupt period. After the host has
serviced the interrupt, the interrupt status bit is cleared via an I/O write to the appropriate bit
in the SD I/O card internal registers. The interrupt output of all SD I/O cards is active low and
the application must provide external pull-up resistors on all data lines (SDMMC_D[3:0]).
In SD 1-bit mode pin 8 is dedicated to the interrupt function (IRQ), and there are no timing
constraints on interrupts.
In SD 4-bit mode the host samples the level of pin 8 (SDMMC_D1/IRQ) into the interrupt
detector only during the interrupt period. At all other times, the host interrupt ignores this
value. The interrupt period begins when interrupts are enabled at the card and SDIOEN bit
is set see register settings in
In 4-bit mode the card can generate a synchronous or asynchronous interrupt as indicated
by the card CCCR register SAI and EAI bits.
•
Synchronous interrupt, require the SDMMC_CK to be active.
•
Asynchronous interrupt, can be generated when the SDMMC_CK is stopped, 4 cycles
after the start of the card interrupt period following the last data block.
Secure digital input/output MultiMediaCard interface (SDMMC)
Table 402. SDIO special operation control
Operation mode
Interrupt detection
Suspend/Resume operation
Table
RM0432 Rev 6
402.
1 X X X
X X X X
X 1 0 1
X 1 1 1
X 0 0 1
X 0 1 1
X
X
1
1
1
1
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