ST STM32L4+ Series Reference Manual page 1975

RM0432
SDMMC_CMD output is in the Hi-Z state. Data sent on SDMMC_CMD are synchronous
with the SDMMC_CK according the NEGEDGE register bit see
The Command and Short Response with CRC, the CRC generator calculates the CRC
checksum for all 40 bits before the CRC code. This includes the start bit, transmitter bit,
command index, and command argument (or card status).
For the Long Response the CRC checksum is calculated only over the 120 bits of R2 CID or
CSD. Note that the start bit, transmitter bit and the six reserved bits are not used in the CRC
calculation.
The CRC checksum is a 7-bit value:
CRC[6:0] = Remainder [(M(x) * x
G(x) = x
M(x) = (first bit) * x
Where n = 39 or 119.
The CPSM allows to send a number of specific commands to handle various operating
modes when CPSMEN is set, see
1 x
0 1
0 1
0 0
0 0
0 0
0 0
0 0
0 0
0 0
The Command/Response path implements the status flags and associated clear bits shown
in Table 393:
Secure digital input/output MultiMediaCard interface (SDMMC)
7 3
+ x + 1
n
+ (second bit) * x
Table 392. Specific Commands overview
x x x x x
x x x x x
1 x x x x
1 x x x x
0 1 x x x
0 0 1 1 x
0 0 1 0 x
0 0 0 1 x
0 0 0 0 1
0 0 0 0 0
RM0432 Rev 6
7
) / G(x)]
n-1
+... + (last bit before CRC) * x
Table 392.
Start Voltage Switch Sequence
Start normal boot
Start alternative boot
Stop alternative boot.
Send command with associated data transfer.
e•MMC stream data transfer, command
(STOP_TRANSMISSION) pending until end of data transfer.
e•MMC stream data transfer, command different from
(STOP_TRANSMISSION) pending until end of data transfer.
Send command (STOP_TRANSMISSION), stopping any
ongoing data transmission.
Enter e•MMC wait interrupt (Wait-IRQ) mode.
Any other none specific command
Figure 574.
0
Description
1975/2301
2041