ST STM32L4+ Series Reference Manual page 1981

RM0432
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ReadWait state: the data path ReadWait the bus.
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• Receive state: the data path receives serial data from a card. Pack the data in bytes
and written it to the data FIFO. Depending on the transfer mode selected in the data
control register (DTMODE), the data transfer mode can be either block or stream:
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a)
b)
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Secure digital input/output MultiMediaCard interface (SDMMC)
- When DATACOUNT = 0, the transfer is completed normally and there will be no
DHOLD flag.
When DPSM has been started with DTEN, after an error (DTIMEOUT) the DPSM
moves to the Idle state when the FIFO is empty and when IDMAEN = 0 reset with
FIFORST.
The DPSM moves to the Wait_R state when the ReadWait stop bit (RWSTOP) is
set, and start the receive timeout.
If the CPSM Abort signal is set, wait for the FIFO to be empty and when IDMAEN
= 0 reset with FIFORST, then moves to the Idle state and sets the DABORT flag.
In block mode, when the data block size (DBLOCKSIZE) number of data bytes are
received, the DPSM waits until it receives the CRC code.
In SDIO multibyte mode, when the data block size (DATALENGTH) number of
data bytes are received, the DPSM waits until it receives the CRC code.
If the received CRC code matches the internally generated CRC code, the DPSM
moves to the
- Wait_R state when RWSTART= 0 and start the receive timeout.
- ReadWait state when RWSTART = 1 and DATACOUNT > zero, and the
DBCKEND flag is set.
If the received CRC code fails the internally generated CRC code any further data
reception is prevented.
- When not all data has been received (DATACOUNT > 0), the CRC fail status flag
(DCRCFAIL) is set and the DPSM stays in the Receive state.
- When all data has been received (DATACOUNT = 0), wait for the FIFO to be
empty after which the CRC fail status flag (DCRCFAIL) is set and the DPSM
moves to the Idle state.
In stream mode, the DPSM receives data while the data counter DATACOUNT >
0. When the counter is zero, the remaining data in the shift register is written to the
data FIFO, and the DPSM moves to the Wait_R state.
When a FIFO overrun error occurs, the DPSM sets the FIFO overrun error flag
(RXOVERR) and any further data reception is prevented. The DPSM stays in the
Receive state.
When an CPSM_Abort signal is received:.
- If the CPSM_Abort signal is received before the 2 last bits of the data with
DATACOUNT = 0, the transfer is aborted. The remaining data in the shift register
is written to the data FIFO, wait for the FIFO to be empty and when IDMAEN = 0
reset with FIFORST, then the DPSM moves to the Idle state and the DABORT flag
is set.
- If the CPSM_Abort signal is received during or after the 2 last bits of the transfer
with DATACOUNT=0, the transfer is completed normally. The DPSM stays in the
Receive state no DABORT flag is generated.
When DPSM has been started with DTEN, after an error (DCRCFAIL when
DATACOUNT > 0, or RXOVERR) the DPSM moves to the Idle state when the
FIFO is empty and when IDMAEN = 0 reset with FIFORST.
RM0432 Rev 6 1981/2301
2041