ST STM32L4+ Series Reference Manual page 2027

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moves to the Idle state and when there has been no error, and no transmit data transfer

hold, the data status end flag (DATAEND) is set.

Bits 31:25 Reserved, must be kept at reset value.

Bits 24:0 DATACOUNT[24:0]: Data count value

This register should be read only after the data transfer is complete, or hold. When reading

after an error event the read data count value may be different from the real number of data

bytes transfered.

SDMMC status register (SDMMC_STAR)

Address offset: 0x034

Reset value: 0x0000 0000

The SDMMC_STAR register is a read-only register. It contains two types of flag:

Static flags (bits [28, 21, 11:0]): these bits remain asserted until they are cleared by

writing to the SDMMC interrupt Clear register (see SDMMC_ICR)

Dynamic flags (bits [20:12]): these bits change state depending on the state of the

underlying logic (for example, FIFO full and empty flags are asserted and deasserted

as data while written to the FIFO)

Bits 31:29 Reserved, must be kept at reset value.

Bit 28 IDMABTC: IDMA buffer transfer complete

Bit 27 IDMATE: IDMA transfer error

Bit 26 CKSTOP: SDMMC_CK stopped in Voltage switch procedure

Secure digital input/output MultiMediaCard interface (SDMMC)

When read, the number of remaining data bytes to be transferred is returned. Write has no

The interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.

DATACOUNT[15:0]

RM0432 Rev 6

DATACOUNT[24:16]

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