ST STM32L4+ Series Reference Manual page 2005

RM0432
SDMMC_CMD
SDMMC_D0
BUSYD0END
54.6.4 Interrupt mode (Wait-IRQ)
The host and card enter and exit interrupt mode (Wait-IRQ) simultaneously. In interrupt
mode there is no data transfer. The only message allowed is an interrupt service request
response from the card or the host. For the interrupt mode to work correctly the
SDMMC_CK frequency shall be set in accordance with the achievable SDMMC_CMD data
rate in Open Drain mode, which depend on the capacitive load and pull-up resistor. The
CLKDIV shall be set >1, and the SETCLKRX shall select either the sdmmc_io_in_ck or
SDMMC_CLKin source.
The host must ensure that the card is in Standby state before issuing the CMD40
(GO_IRQ_STATE). While waiting for an interrupt response the SDMMC_CK clock signal
must be kept active.
A card in interrupt mode (IRQ state):
•
is waiting for an internal card interrupt event. Once the event occurs, the card starts to
send the interrupt service request response. The response is sent in open-drain mode.
•
while waiting for the internal card interrupt event, the card also monitors the
SDMMC_CMD line for a Start bit. Upon detection of a Start bit the card will abort the
interrupt mode and switch to Standby state.
The host in interrupt mode (CPSM Wait state waiting for interrupt):
•
is waiting for a card interrupt service request response (Start bit).
•
while waiting for a card interrupt service request response the host may abort the
interrupt mode (by clearing the WAITINT register bit), which causes the host to send a
interrupt service request response R5 with RCA = 0x0000 in open-drain mode.
When sending the interrupt service request response, the sender bit-wise monitors the
SDMMC_CMD bit stream. The sender whose interrupt service request response bit does
not correspond to the bit on the SDMMC_CMD line stops sending. In the case of multiple
senders only one will successfully send its full interrupt service request response. i.e. If the
host sends simultaneously, it will lose sending after the transmission bit.
To handle the interrupt mode, the following procedure applies:
Secure digital input/output MultiMediaCard interface (SDMMC)
Figure 593. CMD5 Sleep Awake procedure
V
CC
CMD5
RESP
sleep
BUSY
Transistion phase
Standby state
Off
RM0432 Rev 6
CMD5
RESP
awake
BUSY
Transistion phase
Sleep state Standby state
MSv40943V1
2005/2301
2041