ST STM32L4+ Series Reference Manual page 1995

RM0432
SDMMC_CK
SDMMC_CMD
S
SDMMC_D0
SDMMC_D1
SDMMC_D2
SDMMC_D3
Interrupt period
In SDR50 and DDR50, selected by register bit BUSSPEED, due to propagation delay from
the card to host, the interrupt period is asynchronous.
•
The card interrupt period ends after 0 to 2 SDMMC_CK cycles after the End bit of a
command that transfers data block(s) (Command sent with the CMDTRANS bit is set),
or when the DTEN bit is set. At the host the interrupt period ends after the End bit of a
command that transfers data block(s). A card interrupt issued in the 1 to 2 cycles after
the command End bit are not detected by the host during this interrupt period.
•
The card interrupt period resumes 2 to 4 SDMMC_CK after the completion of the last
data block. The host will resume the interrupt period always 2 cycles after the last data
block.
•
There is NO interrupt period at the data block gap.
Note: DTEN shall not be used to start data transfer with SD and e•MMC cards.
Secure digital input/output MultiMediaCard interface (SDMMC)
Figure 585. Synchronous interrupt period data write
Command data
E S RSP
W
IRQ
E
S Data E
S E
Data
S E
Data
Data1
2 CK
RM0432 Rev 6
S CRC status E S Data
S
Data
S
Data
IRQ
Data1
2 CK
E
E
E
MSv40196V2
1995/2301
2041