ST STM32L4+ Series Reference Manual page 2018

Secure digital input/output MultiMediaCard interface (SDMMC)
54.9.2 SDMMC clock control register (SDMMC_CLKCR)
Address offset: 0x004
Reset value: 0x0000 0000
The SDMMC_CLKCR register controls the SDMMC_CK output clock, the sdmmc_rx_ck
receive clock, and the bus width.
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
WID PWR
Res.
BUS[1:0] SAV
rw rw rw
Bits 31:22 Reserved, must be kept at reset value.
Bits 21:20 SELCLKRX[1:0]: Receive clock selection
Bit 19 BUSSPEED: Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50,
DDR50
Bit 18 DDR: Data rate signaling selection
Bit 17 HWFC_EN: Hardware flow control enable
2018/2301
27 26 25
Res. Res. Res.
11 10 9
Res. Res.
rw
These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0
and DPSMACT = 0)
00: sdmmc_io_in_ck selected as receive clock
01: SDMMC_CKIN feedback clock selected as receive clock
10: Reserved
11: Reserved (select sdmmc_io_in_ck)
This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and
DPSMACT = 0)
0: DS, HS, SDR12, SDR25 bus speed mode selected
1: SDR50, DDR50 bus speed mode selected.
This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and
DPSMACT = 0)
DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1
has no effect when WIDBUS = 00 (1-bit wide bus).
DDR rate shall only be selected with clock division >1. (CLKDIV > 0)
0: SDR Single data rate signaling
1: DDR double data rate signaling
This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and
DPSMACT = 0)
0: Hardware flow control is disabled
1: Hardware flow control is enabled
When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags
change, please see SDMMC status register definition in
24 23 22
Res. Res. Res. SELCLKRX[1:0]
8 7 6
CLKDIV[9:0]
rw rw rw
RM0432 Rev 6
21 20 19 18
BUS
DDR
SPEED
rw rw rw rw
5 4 3 2
rw rw rw rw
Section 54.9.11.
RM0432
17 16
HWFC_ NEG
EN EDGE
rw rw
1 0
rw rw