ST STM32L4+ Series Reference Manual page 1971

RM0432
Pending
DPSM send CMD
or
WAITPEND = 0
•
Idle: The command path is inactive. When the command control register is written and
the enable bit (CPSMEN) is set, the CPSM will activate the SDMMC_CK clock (when
stopped due to power save PWRSAV bit) and moves
–
–
–
•
Send: The command is sent and the CRC is appended.
–
–
–
–
Secure digital input/output MultiMediaCard interface (SDMMC)
Figure 577. Command path state machine (CPSM)
SDMMC_CMD write
and
CPSMEN = 1 and
and
WAITPEND = 1
SDMMC_CMD write
and
CPSMEN = 1
and
BOOTEN = 1
BOOTMODE = 0
Boot
and
BOOTEN = 1
BOOTMODE = 1
to the Send state when WAITPEND = 0 & BOOTEN = 0.
to the Pending state when WAITPEND = 1.
to the boot state when BOOTEN = 1.
When CMDTRANS bit is set or when BOOTEN bit is set and BOOTMODE is
alternative boot, and the DTDIR = receive, the CPSM DataEnable signal will be
issued to the DPSM at the end of the command.
When the CMDTRANS bit is set and the CMDSUSPEND bit is 0 the interrupt
period will be terminated at the end of the command.
When CMDSTOP bit is set the CPSM Abort signal will be issue to the DPSM at the
end of the command.
If no response is expected (WAITRESP = 00) the CPSM will move to the Idle state
and the CMDSENT flag is set. When BOOTMODE = 1 & BOOTEN = 0 the
CMDSENT flag is delayed 56 cycles after the command End bit, otherwise the
Reset
Idle
SDMMC_CMD write
and
CPSMEN = 1
and
WAITPEND = 0
and
BOOTEN = 0
BOOTMODE = 0
and
BOOTEN = 0
Send
RM0432 Rev 6
End of CMD
and
WAITRESP = 00
End of CMD
and
WAITRESP = not 00
End of response
or
CRC status error
Receive
Start bit detected
Wait
MSv40161V1
1971/2301
2041