ST STM32L4+ Series Reference Manual page 1982

Secure digital input/output MultiMediaCard interface (SDMMC)
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Wait_S state: the data path waits for data to be available from the FIFO.
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Note: The DPSM remains in the Wait_S state for at least two clock periods to meet the N
requirements, where N
response and the start of the data transfer from the host.
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Send state: the DPSM starts sending data to a card. Depending on the transfer mode
bit in the data control register, the data transfer mode can be either block, SDIO
multibyte or stream:
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1982/2301
If the data counter DATACOUNT > 0, waits until the data FIFO empty flag
(TXFIFOE) is deasserted and DTHOLD is not set, and moves to the Send state.
if the data counter (DATACOUNT) = 0 the DPSM moves to the Idle state.
- When DTHOLD is disabled, the DATAEND flag is set.
- When DTHOLD is enabled, the DHOLD flag is set.
When DTHOLD is set and the DATACOUNT > 0
- When IDMA is enabled, the DBCKEND flag is set and subsequently the FIFO is
flushed, furthermore the DPSM will move to the Idle state and the DHOLD flag is
set.
- When IDMA is disabled the DBCKEND flag is set. Wait for the FIFO to be reset
by software with FIFORST, then DPSM will move to the Idle state and issues the
DHOLD flag.
When DTHOLD is set and DATACOUNT = 0 the transfer is completed normally.
When receiving the CPSM Abort signal
- If the CPSM_Abort signal is received before the 2 last bits of the data with
DATACOUNT = 0, the transfer is aborted, wait for the FIFO to be empty and when
IDMAEN = 0 reset with FIFORST, then the DPSM moves to the Idle state and sets
the DABORT flag.
- If the CPSM_Abort signal is received during or after the 2 last bits of the transfer
with DATACOUNT=0, normal operation is continued, there will be no DABORT
flag since the transfer has completed normally.
is the number of clock cycles between the reception of the card
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In block mode, when the data block size (DBLOCKSIZE) number of data bytes are
send, the DPSM sends an internally generated CRC code and End bit, and moves
to the Busy state and start the transmit timeout.
In SDIO multibyte mode, when the data block size (DATALENGTH) number of
data bytes are send, the DPSM sends an internally generated CRC code and End
bit, and moves to the Busy state and start the transmit timeout.
In stream mode, the DPSM sends data to a card while the data counter
DATACOUNT > 0. When the data counter reaches zero moves to the Busy state
and start the transmit timeout.
Before sending the last stream Byte according to DATACOUNT, the DPSM issues
a trigger on the sendCMD signal. This signal is used by the CPSM to sent any
pending command. (i.e. CMD12 Stop Transmission command)
If a FIFO underrun error occurs, the DPSM sets the FIFO underrun error flag
(TXUNDERR). The DPSM stays in the Send state.
When receiving the CPSM Abort signal
- If the CPSM_Abort signal is received before the 2 last bits of the transfer with
DATACOUNT=0, the transfer is aborted. The DPSM will sent a last data bit
followed by an End bit. The FIFO will be disabled/flushed, and the DPSM moves
to the Busy state to wait for not busy before setting the DABORT flag.
- If the CPSM_Abort signal is received during or after the 2 last bits of the transfer
RM0432 Rev 6
RM0432
timing
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