ST STM32L4+ Series Reference Manual page 2038

Secure digital input/output MultiMediaCard interface (SDMMC)
54.9.19 SDMMC IDMA buffer 1 base address register
(SDMMC_IDMABASE1R)
Address offset: 0x05C
Reset value: 0x0000 0000
The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer
memory base address.
31 30 29 28
rw rw rw rw
15 14 13 12
rw rw rw rw
Bits 31:0 IDMABASE1[31:0]: Buffer 1 memory base address, shall be word aligned (bit [1:0] are always
0 and read only)
2038/2301
27 26 25
rw rw rw
11 10 9
rw rw rw
This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can
dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer
1 is inactive (IDMABACT = '0').
24 23 22
IDMABASE1[31:16]
rw rw rw
8 7 6
IDMABASE1[15:0]
rw rw rw
RM0432 Rev 6
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
RM0432
17 16
rw rw
1 0
r r