ST STM32L4+ Series Reference Manual page 1992

Secure digital input/output MultiMediaCard interface (SDMMC)
The IDMATE will be generated on an other SDMMC transfer interrupt (TXUNDERR.
RXOVERR, DCRCFAIL, DTIMEOUT, DABORT, DHOLD, or DATAEND).
54.5.7 AHB and SDMMC_CK clock relation
The AHB shall at least have 3x more bandwidth than the SDMMC bus bandwidth i.e. for
SDR50 4-bit mode (50Mbyte/s) the minimum sdmmc_hclk frequency is 37.5MHz
(150Mbyte/s).
SDMMC bus mode
e•MMC DS
e•MMC HS
e•MMC DDR52
SD DS / SDR12
SD HS / SDR25
SD DDR50
SD SDR50
54.5.8 Hardware flow control
The hardware flow control functionality is used to avoid FIFO underrun (TX mode) and
overrun (RX mode) errors.
The behavior is to stop SDMMC_CK during data transfer and freeze the SDMMC state
machines. The data transfer is stalled when the FIFO is unable to transmit or receive data.
The data transfer remains stalled until the transmit FIFO is half full or all data according
DATALENGHT has been stored, or until the receive FIFO is half empty. Only state machines
clocked by SDMMC_CK are frozen, the AHB interfaces are still alive. The FIFO can thus be
filled or emptied even if flow control is activated.
To enable hardware flow control, the HWFC_EN register bit must be set to 1. After reset
hardware flow control is disabled.
54.6 Card functional description
54.6.1 SD I/O mode
The following features are SDMMC specific operations:
•
SDIO interrupts
•
SDIO suspend/resume operation (write and read suspend)
•
SDIO read wait operation by stopping the clock
•
SDIO read wait operation by SDMMC_D2 signaling
1992/2301
Table 401. AHB and SDMMC_CK clock frequency relation
SDMMC bus
width
8
8
8
4
4
4
4
RM0432 Rev 6
Maximum SDMMC_CK
[MHz]
26
52
52
25
50
50
100
RM0432
Minimum AHB clock
[MHz]
19.5
39
78
9.4
18.8
37.5
37.5