ST STM32L4+ Series Reference Manual page 1969

RM0432
Note: The adapter registers and FIFO use the AHB clock domain (sdmmc_hclk). The control unit,
command path and data transmit path use the SDMMC adapter clock domain
(sdmmc_ker_ck). The response path and data receive path use the SDMMC adapter
feedback clock domain from the sdmmc_io_in_ck, or SDMMC_CKIN.
Adapter register block
The adapter register block contains all system control registers, the SDMMC command and
response registers and the data FIFO.
This block also generates the signals from the corresponding bit location in the SDMMC
Clear register that clear the static flags in the SDMMC adapter.
Control unit
The control unit illustrated in
SDMMC_CK clock management with divider, and the I/O direction management.
Registers
sdmmc_ker_ck
The power management subunit disables the card bus output signals during the power-off
and power-up phases.
There are three power phases:
• power-off
•
power-up
• power-on
The clock management subunit uses the sdmmc_ker_ck to generate the SDMMC_CK and
provides the division control. It also takes care of stopping the SDMMC_CK for i.e. flow
control.
The clock outputs are inactive:
•
after reset
•
during the power-off or power-up phases
•
if the power saving mode (register bit PWRSAV) is enabled and the card bus is in the
Idle state for eight clock periods. The clock will be stopped eight cycles after both the
command/response CPSM and data path DPSM subunits have enter the Idle phase.
Secure digital input/output MultiMediaCard interface (SDMMC)
Figure 575, contains the power management functions, the
Figure 575. Control unit
Control unit
Power
management
Clock
management
To command/response and data paths
RM0432 Rev 6
SDMMC_D0DIR
SDMMC_D123DIR
IO
management
SDMMC_CDIR
SDMMC_CK
MSv39278V2
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