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TPS65981 USB Type-C

1 Features

This device is certified by the USB-IF for PD2.0
– PD2.0 is no longer certifiable on new designs
as of June 2020
– All new designs requiring certification should
use a PD3.0 compliant device
– Article on
PD2.0 vs PD3.0
Fully configurable USB PD controller
– Control for external DC/DC supplies through
GPIO
Ex:
TPS65981EVM
– Port data multiplexer
USB 2.0 HS data and low speed endpoint
Sideband-use data for alternate modes
GUI tool
to easily configure TPS65981 for
various applications
– Support for DisplayPort alternate mode
– Supports industrial temperature range
– For a more extensive selection guide and
getting started information, please refer to
www.ti.com/usb-c
and
Integrated fully managed power paths:
– Integrated 5-V, 3-A, 55-mΩ sourcing switch
– Integrated 5-V to 20-V, 3-A, 95-mΩ bi-
directional load switch
– Gate Control and current sense for external 5-V
to 20-V, 5-A bidirectional switch (back-to back
NFETs)
– UL2367 cert#: E169910-20150728
Integrated robust power path protection
– Integrated reverse current protection,
undervoltage protection, overvoltage protection,
and slew rate control the high-voltage bi-
directional power path
– Integrated undervoltage and overvoltage
protection and current limiting for inrush current
protection for the 5-V/3-A source power path
USB Type-C
®
Power Delivery (PD) controller
– 8 configurable GPIOs
– BC1.2 charging support
– USB PD 2.0 certified
– USB Type-C specification certified
– Cable attach and orientation detection
– Integrated VCONN switch
– Physical layer and policy engine
– 3.3-V LDO output for dead battery support
– Power supply from 3.3 V or VBUS source
– 1 I2C primary port
– 1 I2C secondary port
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
®
and USB PD Controller, Power Switch, and High Speed
Multiplexer
E2E guide
SLVSDC2C – FEBRUARY 2016 – REVISED AUGUST 2021

2 Applications

After-market automotive infotainment
Other personal electronics and industrial
applications
Medical equipment
Rugged PC and laptop
Docking station
Flat panel monitor

3 Description

The TPS65981 is a highly integrated stand-alone
USB Type-C and Power Delivery (PD) controller
optimized for notebook applications. The TPS65981
integrates fully managed power paths with robust
protection for a complete USB-C PD solution. The
TPS65981 integrates a high speed multiplexer which
is dependent the USB Type-C cable orientation
that the CC pins provide. The multiplexer passes
through side-band use data for alternate modes.
The TPS65981 has a QFN package for reliable
manufacturing with 0.5-mm Pitch and 2-Layer
PCB compatibility and has an extended (industrial)
temperature range. The TPS65981 is USB PD 2.0
certified which is no longer certifiable through USB IF.
Device Information
PART NUMBER
PACKAGE
TPS65981
VQFN (56)
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
5 to 20 V
External FET Sense and CTRL
5 to 20 V
3 A
5 V
3 A
3.3 V
Type-
Host
Detection
Host
Interface
USB PD Controller
High
USB2.0 and
Speed
Sideband-Use
Mux
Data
Alternate Mode Mux Ctrl
TPS65981
SuperSpeed Mux
Copyright © 2016, Texas Instruments Incorporated
Simplified Diagram
TPS65981
(1)
BODY SIZE (NOM)
8.00 mm × 8.00 mm
5 A
V
BUS
C Cable
CC/V
and
CC1/2
2
CONN
USB
Type-C
Connector
USB_TP/TN
2
USB_BP/BN
2
SBU1/2
SBU1/2
2
GND

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Table of Contents
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Summary of Contents for Texas Instruments TPS65981EVM

  • Page 1: Features

    – USB Type-C specification certified – Cable attach and orientation detection SuperSpeed Mux – Integrated VCONN switch Copyright © 2016, Texas Instruments Incorporated – Physical layer and policy engine Simplified Diagram – 3.3-V LDO output for dead battery support – Power supply from 3.3 V or VBUS source –...
  • Page 2: Table Of Contents

    Updated the Description section.........................1 Changes from Revision A (April 2016) to Revision B (August 2016) Page • Changed the device status from Product Preview to Production Data .............. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 3: Description (Continued)

    (DisplayPort, for example). The power-management circuitry uses 3.3 V inside the system and also uses VBUS to start up and negotiate power for a dead-battery or no-battery condition. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 4: Pin Configuration And Functions

    Digital Core I/O and General-purpose digital I/O 16. At power-up, pin state is sensed DEBUG_CTL1 Digital I/O Hi-Z Control to determine bit 4 of the I2C address. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 5 GND. Tie pin to GND when unused 5-V supply for C_CC pins. Bypass with capacitance CPP_CABLE PP_CABLE High Current Power to GND when not tied to PP_5V0. Tie pin to PP_5V0 when unused. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65981...
  • Page 6 Ground. Connect directly to ground plane in accordance with the GND (Thermal Pad) Ground Ground Hi-Z guidelines listed in the Layout Guidelines section to achieve the measured values in the Thermal Information table. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 7: Specifications

    JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 8: Recommended Operating Conditions

    Junction-to-board characterization parameter °C/W Junction-to-case (bottom) thermal resistance °C/W θJC(bottom) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 9: Power Supply Requirements And Characteristics

    I/O buffers are not fail-safe to LDO_3V3. Therefore, VDDIO may power-up before LDO_3V3. When VDDIO powers up before LDO_3V3, the I/Os shall not be driven high. When VDDIO is low and LDO_3V3 is high, the I/Os may be driven high. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback...
  • Page 10: Power Supervisor Characteristics

    Application code can result in other power consumption measurements by adjusting enabled circuitry and clock rates. Application code also provisions the wake=up mechanisms (for example, I C activity and GPIO activity). Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 11: Cable Detection Characteristics

    Threshold voltage of the pull-down FET in series with RD during VTH_DB I_CC = 80 μA dead battery R_RPD Resistance between RPD_Gn and the gate of the pull-down FET MΩ Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65981...
  • Page 12: Characteristics

    TTRANWIN. After waiting TTRANWIN without detecting NCOUNT transitions, the bus is declared idle. Broadband noise ingression is because of coupling in the cable interconnect. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 13: Parameter

    Configured as sink; EN_HV = 1 IHVEXTSD Shutdown quiescent current from SENSEP pin EN_HV = 0 μA IPP5VACT Active quiescent current from PP_5V0 IPP5VSD Shutdown quiescent current from PP_5V0 μA Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65981...
  • Page 14 2.516 2.796 3.075 PP_5V0 current limit, setting 13 2.642 2.936 3.229 PP_5V0 current limit, setting 14 2.768 3.075 3.383 PP_5V0 current limit, setting 15 3.019 3.355 3.69 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 15 Voltage on PP_HV or PP_HVEXT above which VSO_HV the PP_HV or PP_EXT to PP_5V0 transition on VBUS will meet transition requirements Maximum slew rate for positive voltage 0.03 V/μs SRPOS transitions Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65981...
  • Page 16 = 20 mA On resistance difference between P and N paths of AUX_ROND = 1 V to 3.3 V, I = 20 mA –0.25 0.25 Ω AUX_P/N to C_SBU1/2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 17: Requirements

    = –40°C to +105°C unless otherwise noted PARAMETER TEST CONDITIONS UNIT VIH_PORT Port-switch detect input-high voltage LDO_3V3 = 3.3 V VIL_PORT Port-switch detect input-low voltage LDO_3V3 = 3.3 V Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65981...
  • Page 18: Requirements And Characteristics

    7.18 Analog-to-Digital Converter (ADC) Characteristics Recommended operating conditions; T = –40°C to +105°C unless otherwise noted PARAMETER TEST CONDITIONS UNIT RES_ADC ADC current bits F_ADC ADC clock frequency 1.477 1.523 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 19: Characteristics

    Low-level input voltage LDO_3V3 = 3.3 V SWDCL_THI SWDIOCLK HIGH period 0.05 μs SWDCL_TLO SWDIOCLK LOW period 0.05 μs SWDCL_HYS Input hysteresis voltage LDO_3V3 = 3.3 V Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65981...
  • Page 20: I 2 C Slave Requirements And Characteristics

    VDDIO = 1.8 V 0.09 C pulse width suppressed Pin Capacitance SDA AND SCL STANDARD MODE CHARACTERISTICS FSCL C clock frequency THIGH C clock high time μs Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 21: Spi Controller Characteristics

    = 5 pF to 50 pF, TRSPI SPI_CSZ/CLK/PICO rise time LDO_3V3 = 3.3 V 90% to 10%, C = 5 pF to 50 pF, TFSPI SPI_CSZ/CLK/PICO fall time LDO_3V3 = 3.3 V Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65981...
  • Page 22: Buspowerz Configuration Requirements

    DP SINK SIDE (HPD RX) HPD_HDB_SEL = 0 μs T_HPD_HDB HPD high de-bounce time HPD_HDB_SEL = 1 T_HPD_LDB HPD low de-bounce time μs T_HPD_IRQ HPD IRQ limit time 1.35 1.65 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 23: Oscillator Requirements And Characteristics

    Temperature (qC) D002 D001 Figure 7-2. PP_HV Switch On-Resistance vs Figure 7-1. PP_5V0 Switch On-Resistance vs Temperature Temperature Temperature (qC) D003 Figure 7-3. PP_CABLE Switch On-Resistance vs Temperature Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65981...
  • Page 24: Parameter Measurement Information

    Figure 8-2. ADC Enable and Conversion Timing T_SAMPA T_CONVERTA T_INTA T_SAMPLE T_CONVERTA ADC Clock ADC Sample ADC Interrupt New Valid Output New Valid Output ADC Output Figure 8-3. ADC Repeated Conversion Timing Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 25 Valid Data t hdpoci Figure 8-5. SPI Controller Timing whigh wlow SWD_CLK dout dout SWD_DATA (Output) Valid Data hdin suin SWD_DATA (Input) Valid Data Figure 8-6. SWD Timing Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65981...
  • Page 26: Detailed Description

    The TPS65981 also integrates a thermal shutdown mechanism (see Thermal Shutdown section) and runs off of accurate clocks provided by the integrated oscillators (see the Oscillators section). Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 27: Functional Block Diagram

    Cable and Device GPIO0,2-8 C_CC1 Detect, I2C_SDA/SCL/IRQ1Z RPD_G1 Digital Core Cable Power, C_CC2 SPI_PICO/POCI/CSZ/CLK RPD_G2 USB-PD Phy SWD_DAT/CLK DEBUG_CTL1/2 C_USB_TP/TN AUX_P/N C_USB_BP/BN Port Data Multiplexer USB_RP_P/N C_SBU1/2 DEBUG1 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65981...
  • Page 28: Feature Description

    USB-PD transmitter. Figure 9-3 illustrates the high-level block diagram of the baseband USB-PD receiver. 4b5b Data to PD_TX Encoder Encoder Figure 9-2. USB-PD Baseband Transmitter Block Diagram Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 29 C_CCn DC bias while transmitting, but will return to a Hi-Z state allowing the DC voltage to return to the C_CCn pin when not transmitting. Figure 9-5 shows the USB-PD BMC TX/Rx driver block diagram. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65981...
  • Page 30 Digitally Adjustable VREF USB-PD Modem Copyright © 2016, Texas Instruments Incorporated Figure 9-5. USB-PD BMC TX/Rx Block Diagram Figure 9-6 shows the transmission of the BMC data on top of the DC bias. Note, The DC bias can be anywhere...
  • Page 31 C_CC2 pins. When in a disconnected state, the TPS65981 monitors the voltages on these pins to determine what, if anything, is connected. See the USB Type-C Specification for more information. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65981...
  • Page 32 RD will be RD_CC; however, while dead-battery or no-battery conditions exist, the resistance is un-trimmed and will be RD_DB. When RD_DB is presented during dead-battery or no-battery, application code will switch to RD_CC. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 33 PP_CABLE to C_CC1 or C_CC2. The PP_CABLE to C_CCn switches shown in Figure 9-11 are the same as in Figure 9-1, but are now shown without the analog USB Type-C cable plug and orientation detection circuitry. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65981...
  • Page 34 Figure 9-12 shows the I-V characteristics of the reverse current protection feature. Figure 9-12 and the reverse current limit can be approximated using Equation IREV5V0 = VREV5V0/RPP5V Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 35 2 Ω. I VBUS VBUS Time (5 Ps/div) D004 Figure 9-13. PP_5V0 Current Limit with a Hard Short Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65981...
  • Page 36 The TPS65981 provides power from PP_HV to VBUS at the USB Type-C port as an output when operating as a source. When the switch is on as a source, the path behaves resistively until the current reaches the amount Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 37 Figure 9-19 shows the approximate response time and clamping characteristics for a soft short of 7 Ω. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65981...
  • Page 38 VBUS to PP_EXT to charge a battery when the TPS65981 is acting as a sink. The internal and external paths must never be used in parallel to source current at the same Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 39 VBUS and SENSEP pins monitor the voltage across the NFETs. To ensure that SENSEN does not float, tie SENSEP to SENSEN in this configuration. When configured in this mode, the digital readout from current from the ADC will be approximately zero. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 40 MAnagement) and execute boot code (see Boot Code). The boot code will observe the BUSPOWERZ voltage, which will fall into one of three voltage ranges: VBPZ_DIS, VBPZ_HV, and VBPZ_EXT (defined in Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 41 The voltage ramp will remain monotonic until the voltage reaches VSRCVALID within the final voltage. The voltage may overshoot the new voltage by VSRCVALID. After time TSTABLE from the Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback...
  • Page 42 VBUS. The amplifier implements active slew rate control by adjusting the pull-down current to prevent the slew rate from exceeding specification. When VBUS falls to within VHVDISPD Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 43 See the Section 9.3.2 section for more detailed information on plug and orientation detection. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65981...
  • Page 44 C_CC1 USB-PD Digital Core Power LDO_3V3 C_CC2 VCONN Active Cable Circuitry Cable Plug C_CC2 Gate Control Figure 9-29. Port C_CC1 and C_CC2 Normal Orientation Power from PP_CABLE Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 45 The switch does not have reverse current blocking when the switch is enabled and current is flowing to either C_CC1 or C_CC2. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 46 Figure 9-31. PP_CABLE to C_CCn Current Limit With a Hard Short I CC2 C_CC2 PP_CABLE Time (500 Ps/div) D010 Figure 9-32. PP_CABLE to C_CCn Current Limit With a Hard Short (Extended Time Base) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 47 VBUS (A4, A9, B4, B9) C_CC1 CC1 (A5) C_CC2 CC2 (B5) C_USB_TP D+ (A6) C_USB_TN D– (A7) C_USB_BP D+ (B6) C_USB_BN D– (B7) C_SBU1 SBU1 (A8) C_SBU2 SBU2 (B8) Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65981...
  • Page 48 SBU_INT2 C_SBU2 DEBUG1 AUX_P/N Copyright © 2016, Texas Instruments Incorporated Figure 9-35. Port Data Multiplexers Table 9-3 shows the typical signal types through the switch path. All switches are analog pass switches. These switch paths are not limited to the specified signal type. For the signals that interface with the digital core, the maximum data rate is dictated by the clock rate at which the core is running.
  • Page 49 The TPS65981 has pull-ups and pull-downs between the first and second stage multiplexers of the port switch for each port output: C_SBU1/2, C_USB_TP/N, C_USB_BP/N. The configurable pull-up and pull-down resistances between each multiplexer are shown in Figure 9-36. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65981...
  • Page 50 USB-Billboard information to a host system as defined in the USB Type-C standard. EP0 is used for advertising the Billboard Class. When a host is connected to a device that provides Alternate Modes which Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 51 D+/D– pins is a charger. To enable the required detection mechanisms, the block integrates various voltage sources, currents, and resistances to the Port Data Multiplexers. Figure 9-39 shows the connections of these elements to the Port Data Multiplexers. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65981...
  • Page 52 TPS65982) is an internal reference voltage that is enabled when VIN_3V3 rises above the under-voltage threshold and application code is executing, causing RESETZ to be de-asserted. Figure 9-40 shows the power supply path. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 53 VREF LDO_1V8A LDO_1V8D_EN Copyright © 2016, Texas Instruments Incorporated Figure 9-40. Power Supply Path The TPS65981 is powered from either VIN_3V3 or VBUS. The normal power supply input is VIN_3V3. In this mode, current flows from VIN_3V3 to LDO_3V3 to power the core 3.3-V circuitry and the 3.3-V I/Os. A second LDO steps the voltage down from LDO_3V3 to LDO_1V8D and LDO_1V8A to power the 1.8-V core digital...
  • Page 54 Thermal Shutdown USB EP USB EP Copyright © 2016, Texas Instruments Incorporated Figure 9-41. Digital Core Block Diagram 9.3.7 USB-PD BMC Modem Interface The USB-PD BMC modem interface is a fully USB-PD compliant Type-C interface. The modem contains the BMC encoder and decoder, the TX/Rx FIFOs, the packet engine for construction and deconstruction of the USB-PD packet.
  • Page 55 Table 9-5. HPD GPIO Configuration HPD (Binary) Configuration GPIO4 GPIO5 HPD TX Generic GPIO HPD RX Generic GPIO HPD TX HPD RX HPD TX/RX (bidirectional) Generic GPIO Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65981...
  • Page 56 Debounce State HPD_IRQ Interrupt Timer passes Low_Debounce Timer Passes S4: HPD IRQ IRQ_Limit HPD GPIO goes Detect State high before Timer reaches IRQ_Limit Figure 9-42. HPD RX Flow Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 57 ADC. For the external FET path, the difference in the SENSEP and SENSEN voltages is converted to detect the current (I_PP_EXT) that is sourced through this path. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback...
  • Page 58 Voltage IPP_CABLE Current CC2_BY5 Voltage GPIO5 Voltage CC1_BY2 Voltage CC2_BY2 Voltage PP_CABLE Voltage VIN_3V3 Voltage VRSTZ_3V3 Voltage BC_ID Voltage LDO_1V8A Voltage LDO_1V8D Voltage LDO_3V3 Voltage Unused Voltage Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 59 The One Time Automatic Readout mode is identical to the Round-Robin Automatic Readout except the conversion process halts after the final channel is converted. Once all 11 channels are converted, an interrupt occurs to the digital core. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 60 VDDIO is fail-safe and a diode will not be present from GPIOn to VDDIO in this configuration. The pull-up and pull-down output drivers are independently controlled from the input and are enabled or disabled via application code in the digital core. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 61 IOBUF_GPIOLSI2C that is identical to IOBUF_GPIOLS with an extended de-glitch time. LDO_3V3 GPIO_OD_EN GPIO_OE GPIO_DO GPIO_PU_EN GPIO_RPU GPIO_RPD GPIO_PD_EN 50 ns DEBUG_CTL1/2 GPIO_DI Deglitch GPIO_AI_EN To ADC Figure 9-46. IOBUF_GPIOLSI2C (General GPIO) I/O with I C De-glitch Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65981...
  • Page 62 I2C_IRQnZ I2C_DO Figure 9-49. IOBUF_I2C I/O 9.3.17.5 IOBUF_GPIOHSPI Figure 9-50 shows the I/O buffers for the SPI interface. SPI_x SPIin CMOS SPIout Output SPI_OE Figure 9-50. IOBUF_GPIOHSSPI Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 63: Device Functional Modes

    Once initial device configuration is complete the boot code determines if the TPS65981 is booting under dead battery condition (VIN_3V3 invalid, VBUS valid). If the boot code determines the TPS65981 is booting under Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback...
  • Page 64 Once the I C addresses are established the TPS65981 enables a limited host interface to allow for communication with the device during the boot process. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 65 The state of the BUSPOWERZ pin is read to determine power path configuration for dead battery operation. After the power path is configured, the TPS65981 will continue through the boot process. Figure 9-54 depicts the full dead battery process. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65981...
  • Page 66 For example, if a power loss occurred while writing new code, the original code is still in place and used at the next boot. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 67 If both regions contain invalid data the device carries out the Invalid Memory flow. Figure 9-56 shows the flow of the flash memory read. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65981...
  • Page 68 If the flash memory read fails because of invalid data, the TPS65981 carries out the memory invalid flow and presents the SWD interface on the USB Type-C SBU pins. Memory Invalid Flow depicts the invalid memory process. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 69: Programming

    C slave. An interrupt mask is set for the I C port that determines what events are interrupted on the port. The interrupt mask is configurable in application code. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 70 ACK or NACK at the last clock pulse. Start Condition Stop Condition Figure 9-58. I C Definition of Start and Stop Conditions Data Line Change Figure 9-59. I C Bit Transfer Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 71 Unique Address Register Number Byte Count = N Data Byte 1 Data Byte 2 Data Byte N Figure 9-61. I C Unique Address Write Register Protocol Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65981...
  • Page 72 GPIO and the address decoding is done by firmware in the digital core. To Address Decoder DEBUG_CTL1 Tristate DEBUG_CTL2 Debug Data To Address Decoder Figure 9-64. I C Address Decode Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 73: Application And Implementation

    SBU1/2 VIN_3V3 Supply 3.3 V, 50 mA GPIOx SSTX/RX GPIOy Copyright © 2016, Texas Instruments Incorporated *12 Volt supply is optional Figure 10-1. Type-C and PD Charger Application Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 74 Pull-ups on the I2C_CLK, I2C_SDA, and I2C_IRQZ are used for debugging purposes. In most simple charger designs, I C communication is not needed in the final application. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 75 1-µF capacitor. In this design LDO_3V3 powers the external flash and various pull-ups of the TPS65981 device. A 10-µF capacitor was chosen to support these additional connections. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 76 HD3SS460 SuperSpeed signal pairs for 2-lanes of USB3 data and 2-lanes of DisplayPort video or 4-lanes of DisplayPort video depending on the Alternate Mode configured by the downstream-facing port (DFP). Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 77 ML0 – ML3 ML0 – ML3 or Scalar) 2 or 4 Lane DP Copyright © 2016, Texas Instruments Incorporated Figure 10-3. Type-C and PD Dock or Monitor Application 10.2.2.1 Design Requirements For a USB Type-C and PD dock application, Table 10-3...
  • Page 78 Figure 10-4. DC Barrel Jack Voltage Divider DC Barrel Jack Voltage 1.8 V 100 kΩ Barrel Jack Detect/ PFET Enable 10 kΩ Figure 10-5. Barrel Jack Detect Comparator Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 79 TPS65981. In a dock or monitor application, the video scalar is commonly a processor and the I C master capable of acting as the system controller for the TPS65981. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 80: Power Supply Recommendations

    Internal circuitry is powered from 1.8 V. There are two LDOs that step the voltage down from LDO_3V3 to 1.8 V. One LDO powers the internal digital circuits. The other LDO powers internal low voltage analog circuits. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 81: Vddio

    To prevent the possibility of large ground currents into the TPS65981 during sudden disconnects because of inductive effects in a cable, TI recommends that a Schottky be placed from VBUS to GND as shown in Figure 11-1. The NSR20F30NXT5G is recommended. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65981...
  • Page 82: Layout

    PCB. This footprint is available for download on the TPS65981 product folder on the TPS65981 product folder. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 83 TPS65981 www.ti.com SLVSDC2C – FEBRUARY 2016 – REVISED AUGUST 2021 Copyright © 2016, Texas Instruments Incorporated Figure 12-1. Top View Standard TPS65981 Footprint Figure 12-2. Recommended Minimum Via Size 12.1.2 Top TPS65981 Placement and Bottom Component Placement and Layout When the TPS65981 is placed on top and the components on bottom the solution size will be the smallest. For systems that do not use the optional external FET path the solution size will average less than 100 mm mm ×...
  • Page 84 The bottom layer has most of the components placed and routed already. Place a polygon pour to connect all of the GND nets and vias on the bottom layer, refer to Figure 12-14. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 85: Layout Example

    SLVSDC2C – FEBRUARY 2016 – REVISED AUGUST 2021 12.2 Layout Example Copyright © 2016, Texas Instruments Incorporated Figure 12-3. Example Layout (Top View in 2-D) Copyright © 2016, Texas Instruments Incorporated Figure 12-4. Example Layout (Bottom View in 2-D) Copyright ©...
  • Page 86 TPS65981 www.ti.com SLVSDC2C – FEBRUARY 2016 – REVISED AUGUST 2021 Copyright © 2016, Texas Instruments Incorporated Figure 12-5. Example Layout (Top View in 3-D) Copyright © 2016, Texas Instruments Incorporated Figure 12-6. Example Layout (Bottom View in 3-D) Copyright © 2016, Texas Instruments Incorporated Figure 12-7.
  • Page 87 TPS65981 www.ti.com SLVSDC2C – FEBRUARY 2016 – REVISED AUGUST 2021 Copyright © 2016, Texas Instruments Incorporated Figure 12-8. Bottom Polygonal Pours Copyright © 2016, Texas Instruments Incorporated Figure 12-9. CC1 and CC2 Capacitor Routing Copyright © 2021 Texas Instruments Incorporated...
  • Page 88 TPS65981 www.ti.com SLVSDC2C – FEBRUARY 2016 – REVISED AUGUST 2021 Copyright © 2016, Texas Instruments Incorporated Figure 12-10. Top Layer Component Routing Copyright © 2016, Texas Instruments Incorporated Figure 12-11. Bottom Layer Component Routing Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated...
  • Page 89 TPS65981 www.ti.com SLVSDC2C – FEBRUARY 2016 – REVISED AUGUST 2021 Copyright © 2016, Texas Instruments Incorporated Figure 12-12. Final Routing (Top Layer) Copyright © 2016, Texas Instruments Incorporated Figure 12-13. Final Routing (Inner Signal Layer) Copyright © 2016, Texas Instruments Incorporated Figure 12-14.
  • Page 90: 13 Device And Documentation Support

    All trademarks are the property of their respective owners. 13.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
  • Page 91 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 92 4222809/A 03/2016 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.
  • Page 93 SCALE:12X 4222809/A 03/2016 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65981...
  • Page 94 PACKAGE OPTION ADDENDUM www.ti.com 1-Mar-2023 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing Ball material (4/5) TPS65981ABIRTQR NRND 2000 RoHS & Green NIPDAUAG Level-3-260C-168 HR -40 to 85 65981ABI TPS65981ABIRTQT...
  • Page 95 PACKAGE OPTION ADDENDUM www.ti.com 1-Mar-2023 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2...
  • Page 96 PACKAGE MATERIALS INFORMATION www.ti.com 28-Aug-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Reel Reel Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) TPS65981ABIRTQR 2000 330.0 16.4 12.0 16.0 TPS65981ABIRTQT 180.0 16.4 12.0...
  • Page 97 PACKAGE MATERIALS INFORMATION www.ti.com 28-Aug-2017 *All dimensions are nominal Device Package Type Package Drawing Pins Length (mm) Width (mm) Height (mm) TPS65981ABIRTQR 2000 367.0 367.0 38.0 TPS65981ABIRTQT 210.0 185.0 35.0 TPS65981ABTRTQR 2000 367.0 367.0 38.0 TPS65981ABTRTQT 210.0 185.0 35.0 Pack Materials-Page 2...
  • Page 98 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated...
  • Page 99 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments TPS65981ABIRTQR TPS65981ABTRTQR TPS65981ABIRTQT TPS65981ABTRTQT...

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