Texas Instruments AFE 32A3W Series Manual
Texas Instruments AFE 32A3W Series Manual

Texas Instruments AFE 32A3W Series Manual

10-bit and 8-bit, three-channel voltage-output, current-output, and adc-input smart afe with i2c or spi
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AFEx32A3W 10-Bit and 8-Bit, Three-Channel Voltage-Output, Current-Output, and

1 Features

Current-source DAC:
– 1-LSB DNL
– Two ranges: 300 mA and 220 mA
– 770-mV headroom
Dual voltage-output DACs:
– 1-LSB DNL
– Gains of 1 ×, 1.5 ×, 2 ×, 3 ×, and 4 ×
ADC input on channel 1
Programmable comparator mode on channel 1
High-impedance output when VDD is off
High-impedance and resistive pulldown power-
down modes
50-MHz SPI-compatible interface
Automatically detects I
– 1.62-V V
with V
IH
DD
General-purpose input/output (GPIO) configurable
as multiple functions
Predefined waveform generation: sine, cosine,
triangular, sawtooth
User-programmable nonvolatile memory (NVM)
Internal or power-supply as reference
Wide operating range:
– Power supply: 3 V to 5.5 V
– Temperature: –40˚C to +125˚C

2 Applications

Optical module
Laser
LOW
Figure 3-1. Electro-absorption Modulated Laser (EML) Control Using AFEx32A3W
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADC-Input Smart AFE With I
2
C or SPI
= 5.5 V
1.5
F
100 nF
¡
CAP
LDO
NVM
BUFFER
SDA/SCLK
A0/SDI
SCL/SYNC
HIGH
BUFFER
GPIO/SDO
BUFFER
Output Configuration
Logic
AGND
2
C or SPI

3 Description

The 10-bit AFE532A3W and the 8-bit AFE432A3W
(AFEx32A3W) are a three-channel, buffered voltage-
output, current-output, and ADC-input smart analog
front end (AFE). The AFEx32A3W devices support
a current source that can be used for linear
control of laser diodes and miniature motors. These
devices support Hi-Z power-down mode and Hi-
Z output during power-off conditions for voltage
output. Channel 1 can be configured as an ADC,
voltage-output DAC or a comparator. The voltage-
output DACs provide a force-sense option for use
as a programmable comparator and current sink.
The multifunction GPIO, function generation, and
programmable nonvolatile memory (NVM) enable
these smart AFEs for processor-less applications and
design reuse. These devices automatically detect SPI
2
or I
C interfaces and contain an internal reference.
The AFEx32A3W feature set combined with the tiny
package and low power make these smart AFEs an
excellent choice for applications such as laser diode
power control and electro-absorption modulated laser
(EML) control in passive optical network (PON) and
other industrial laser applications.
Device Information
PART NUMBER
AFE532A3W
YBH (DSBGA, 16)
AFE432A3W
YBH (DSBGA, 16)
(1)
For more information see
(2)
The package size (length × width) is a nominal value and
includes pins, where applicable.
V
DD
V
PV
DD
DD
Internal
Reference
EML
IDAC
10 k
10 k
V
¢
SS
VOUT
EAM
+
VDD
10 k
£
ADC
FB1
AFEx32A3W
PGND
AFE532A3W, AFE432A3W
SLASFB2 – NOVEMBER 2023
(1)
PACKAGE
PACKAGE SIZE
1.72 mm × 1.72 mm
1.72 mm × 1.72 mm
Section
11.
V
DD
(2)

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Summary of Contents for Texas Instruments AFE 32A3W Series

  • Page 1: Features

    AFE532A3W, AFE432A3W SLASFB2 – NOVEMBER 2023 AFEx32A3W 10-Bit and 8-Bit, Three-Channel Voltage-Output, Current-Output, and ADC-Input Smart AFE With I C or SPI 1 Features 3 Description • Current-source DAC: The 10-bit AFE532A3W and the 8-bit AFE432A3W (AFEx32A3W) are a three-channel, buffered voltage- –...
  • Page 2: Table Of Contents

    7.9 DAC-1-GAIN-CMP-CONFIG Register (address = Glossary..............85 15h) [reset = 0000h]............ 10 Revision History............7.10 DAC-2-GAIN-CONFIG Register (address = 11 Mechanical, Packaging, and Orderable 03h) [reset = 0000h]............ Information..............Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 3: Pin Configuration And Functions

    C serial data bus or SPI clock input. This pin must be connected to the I/O voltage using an external SDA/SCLK Input/Output pullup resistor in the I C mode. This pin can ramp up before VDD. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 4: Specifications

    Junction-to-top characterization parameter °C/W Ψ Junction-to-board characterization parameter 20.3 °C/W For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 5: Electrical Characteristics: Voltage Output

    , gain = 3 × or 4 × Power-supply rejection ratio Internal V , gain = 2 ×, DAC at midscale, 0.25 mV/V (dc) = 5 V ±10% Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 6 Specified with 200-mV headroom with respect to reference value when internal reference is used. The total power consumption is calculated by I × (total number of channels powered on) + (sleep-mode current). Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 7: Electrical Characteristics: Current Output

    DAC channel disabled, voltage across the internal Power-down leakage at output pulldown resistor Power supply rejection ratio DAC at midscale, V changed from 3.5 V to 4.5 V LSB/V (dc) Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 8 These devices do not have automatic thermal shutdown. The external circuitry must maintain the junction temperature within the specified limits. The current flowing into V does not account for the load current sourced or sinked on the IOUT pins. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 9: Electrical Characteristics: Comparator Mode

    ADC averaging setting is 4 samples 1406 2008 Sampling capacitor Specified by design and characterization, not production tested. Measured at DAC at mid-scale, comparator input at Hi-Z. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 10: Electrical Characteristics: General

    ±2 µA resistance of 10 kΩ at OUT pin Specified by design and characterization, not production tested. Measured at –40°C and +125°C and calculated the slope. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 11: Timing Requirements: I C Standard Mode

    0.45 µs VDDAT trace probe Data valid acknowledge time, R = 360 Ω, C = 23 pF, C = 10 pF 0.45 µs VDACK trace probe Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 12: Timing Requirements: Spi Write Operation

    SCLK falling edge to SYNC rising edge SYNC high time µs CSHIGH SCLK rising edge to SDO falling edge, I ≤ 5 mA, C = 20 pF. SDODLY Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 13: Timing Requirements: Gpio

    SUSTA HDSTA VDACK SUSTO clock pulse GPIO/ LDAC STP2LDAC LDACW S: Start bit, Sr: Repeated start bit, P: Stop bit Figure 5-1. I C Timing Diagram Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 14 Data From First Read Command Bit 23 Bit 1 Bit 0 FSDO = 1 SDODLY Data From First Read Command Figure 5-3. SPI Read Timing Diagram Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 15: Typical Characteristics: Voltage Output

    Code Code Internal reference, gain = 4 × Figure 5-9. Voltage Output DNL vs Digital Input Code Figure 5-8. Voltage Output DNL vs Digital Input Code Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 16 Supply Voltage (V) DAC channels at midscale DAC channels at midscale Figure 5-14. Voltage Output TUE vs Temperature Figure 5-15. Voltage Output TUE vs Supply Voltage Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 17 10 2030 50 100 200 500 1000 10000 100000 Frequency (Hz) Time (s) Figure 5-18. Voltage Output AC PSRR vs Frequency Figure 5-19. Voltage Output Code-to-Code Glitch - Rising Edge Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 18 DAC in Hi-Z power-down mode Full scale to zero scale swing Figure 5-23. Voltage Output Power-On Glitch Figure 5-22. Voltage Output Setting Time - Falling Edge Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 19 Figure 5-26. Voltage Output Noise Density Figure 5-27. Voltage Output Flicker Noise Channel 0 Channel 1 Time (s) f = 0.1 Hz to 10 Hz Figure 5-28. Voltage Output Flicker Noise Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 20: Typical Characteristics: Current Output

    -0.25 -0.4 -0.5 -0.6 -0.75 -0.8 Temperature (°C) Supply Voltage (V) Figure 5-33. Current Output DNL vs Temperature Figure 5-34. Current Output DNL vs Supply Voltage Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 21 ¼ scale to ¾ scale swing Zero scale to full scale swing Figure 5-39. Current Output Setting Time, Rising Edge Figure 5-40. Current Output Setting Time, Rising Edge Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 22 100000 Frequency (Hz) Inductive load f = 0.1 Hz to 10 Hz, diode load Figure 5-45. Current Output Noise Density Figure 5-46. Current Output Flicker Noise Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 23 Figure 5-47. Current Output Flicker Noise 1000 10 2030 50 100 200 500 1000 10000 100000 Frequency (Hz) Inductive load Figure 5-49. Current Output AC PSRR vs Frequency Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 24: Typical Characteristics: Comparator

    Figure 5-50. Comparator Response Time: Figure 5-51. Comparator Response Time: Low‑to‑High Transition High‑to‑Low Transition -1.2 -2.4 -3.6 -4.8 110 125 Temperature (°C) Figure 5-52. Comparator Offset Error vs Temperature Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 25: Typical Characteristics: Adc

    -0.2 -0.4 -0.6 -0.8 110 125 110 125 Temperature (°C) Temperature (°C) Figure 5-58. ADC Gain Error vs Temperature Figure 5-57. ADC Offset Error vs Temperature Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 26: Typical Characteristics: General

    External Capacitance on CAP Pin (F) Sleep mode, internal reference disabled Figure 5-61. Power-Down Current vs Temperature Figure 5-62. Boot-Up Time vs Capacitance on CAP pin Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 27: Detailed Description

    DAC that depends on a processor to function. As a result of processor-less operation and the smart feature set, the AFEx32A3W is called a smart AFE. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback...
  • Page 28: Functional Block Diagram

    ADC Logic SDA/SCLK GPIO/SDO Power-Down Logic Output Configuration Channel 1 Internal AGND PVDD Reference Register Buffer AMP2 Power-Down Logic AMP1 Output IOUT Configuration Channel 2 AGND PGND Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 29: Feature Description

    GPIO triggers the DAC output without the SPI or I C interface. The integrated functions and the FB1 pin enable PWM output for control applications. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 30 Characteristics: General section provides the timing specification for the NVM write cycle. The processor must wait for the specified duration before resuming any read or write operation on the SPI or I C interface. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 31: Device Functional Modes

    DAC-PDN-0 DAC-PDN-1 VOUT0 DAC Ladder VOUT1/AIN1 – 10 k ¡ 100 k DAC-PDN-0 (Hi-Z) DAC-PDN-1 (Hi-Z) PGND AGND Figure 6-1. Voltage Reference Selection and Power-Down Logic Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 32 DAC-2-DATA register. • GAIN is the value of the IOUT-GAIN setting as specified in the DAC-2-GAIN-CONFIG register. • K is the transfer function constant, 0.5241 (typical). Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 33 0.1 μF 1.5 μF PVDD PVDD VOUT1/AIN1 DAC1 (Optional comparator output) DAC2 IOUT (Comparator input) DAC0 VOUT0 AGND PGND AFEx32A3W 10 kΩ Figure 6-2. Comparator Interface Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 34 Normal comparator mode. No hysteresis or window operation. Hysteresis comparator mode. DAC-1-MARGIN-HIGH and DAC-1-MARGIN-LOW registers set the hysteresis. Window comparator mode. DAC-1-MARGIN-HIGH and DAC-1-MARGIN-LOW registers set the window bounds. Invalid setting Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 35 CMP-1-INV-EN = 0 RESET-CMP-FLAG-1 Figure 6-5. Latching Comparator With Active Low Output DAC-1-MARGIN-HIGH (FULL-CODE) DAC-1-MARGIN-LOW VOUT1/AIN1 CMP-1-INV-EN = 0 RESET-CMP-FLAG-1 Figure 6-6. Latching Comparator With Active High Output Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 36 CONFIG register to get the best response time from the window comparator. • The CMP-1-OUT-EN bit in the DAC-1-GAIN-CMP-CONFIG register can be set to 0b to eliminate undesired toggling of the VOUT1/AIN1 pin. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 37 ADC on channel 1. 0.1 μF 1.5 μF 10 k ¡ PVDD (Optional) PVDD ADC1 VOUT1/AIN1 DAC2 IOUT DAC0 VOUT0 AGND PGND AFEx32A3W 10 k Figure 6-8. ADC Interface Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 38 Read the data from the SRAM-DATA register again to get the MSB bits. 4. Set the EE-READ-ADDR bit to 1b in the COMMON-CONFIG register, to select row2 of the NVM. Repeat steps 2 and 3. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 39 Switch to DAC code stored in NVM (no slew) and then switch to Hi-Z power-down. Slew to margin-low code and then switch to Hi-Z power-down. Slew to margin-high code and then switch to Hi-Z power-down. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 40 MARGIN_HIGH is the decimal value of the DAC-x-MARGIN-HIGH bits in the DAC-x-MARGIN-HIGH register. • MARGIN_LOW is the decimal value of the DAC-x-MARGIN-LOW bits in the DAC-x-MARGIN-LOW register. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 41 12 µs 18 µs 27 µs 40.5 µs 60.75 µs DAC-x-FUNC-CONFIG 91.13 µs 136.69 µs 239.2 µs 418.61 µs 732.56 µs 1281.98 µs 2563.96 µs 5127.92 µs Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 42 FUNCTION_MAX is the decimal value of DAC-x-MARGIN-HIGH bits in the DAC-x-MARGIN-HIGH register. • FUNCTION_MIN is the decimal value of the DAC-x-MARGIN-LOW bits in the DAC-x-MARGIN-LOW register. FUNCTION-MAX TIME-STEP CODE-STEP FUNCTION-MIN Figure 6-11. Triangle Waveform Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 43 FUNCTION_MAX is the decimal value of the DAC-x-MARGIN-HIGH bits in the DAC-x-MARGIN-HIGH register. • FUNCTION_MIN is the decimal value of the DAC-x-MARGIN-LOW bits in the DAC-x-MARGIN-LOW register. FUNCTION-MAX TIME-STEP CODE-STEP FUNCTION-MIN Figure 6-12. Sawtooth Waveform Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 44 6 (90° phase start) 0xE66 0x19A 0xE2F 0x1D1 8 (120° phase start) 0xD8B 0x275 0xC87 0x379 0xB33 0x4CD 0x9A8 0x658 TIME PERIOD Figure 6-13. Sine Wave Generation Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 45 1. However, the software reset function through the COMMON-TRIGGER register is not blocked when using the I C interface. To bypass the DEV-LOCK setting, write 0101b to the DEV-UNLOCK bits in the COMMON-TRIGGER register. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 46 Pull the GPIO/SDO pin high or low when not used. When the GPIO/SDO pin is used as RESET, the configuration must be programmed into the NVM. Otherwise, the setting is cleared after the device resets. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 47 Table 6-10. General-Purpose Output (STATUS) Function Map REGISTER BIT FIELD VALUE FUNCTION 0000 ADC-DRDY 0001 NVM-BUSY 0100 DAC-2-BUSY GPIO-CONFIG GPO-CONFIG 0110 DAC-0-BUSY 0111 DAC-1-BUSY 1011 WIN-CMP-1 Others Not applicable Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 48: Programming

    FIELD DESCRIPTION Echo R/W from previous access cycle 22-16 A[6:0] Echo register address from previous access cycle 15-0 DI[15:0] Readback data requested on previous access cycle Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 49 Device B command Device C command SDI-C D23 – D1 D23 – D1 SDO-C Device A command Device B command Figure 6-18. SPI Daisy-Chain Write Cycle Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 50 Not acknowledge Data output by receiver Acknowledge SCL from controller Clock pulse for acknowledgement Start condition Figure 6-19. Acknowledge and Not Acknowledge on the I C Bus Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 51 Change of data Data line stable allowed Data valid Figure 6-20. Start and Stop Conditions Figure 6-21. Bit Transfer on the I C Bus Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 52 (clock = 1 MHz), the maximum DAC update rate is limited to 25kSPS. When a stop condition is received, the AFEx32A3W device releases the I C bus and awaits a new start condition. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 53 Broadcast is supported only in write mode. 6.5.2.2.2 Command Byte The Register Names table in the Register Map section lists the command byte in the ADDRESS column. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 54 Command byte Address byte MSDB LSDB Section 6.5.2.2.1 Section 6.5.2.2.2 Section 6.5.2.2.1 From controller Target From controller Target From controller Target From target Controller From target Controller Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 55: Register Map

    CONFIG-1 CONFIG-1 DAC-2-FUNC- SYNC- BRD- CLR-SEL-2 FUNC-GEN-CONFIG-BLOCK-1 CONFIG CONFIG-2 CONFIG-2 DAC-0-DATA DAC-0-DATA DAC-1-DATA DAC-1-DATA DAC-2-DATA DAC-2-DATA ADC-CONFIG- RESERVED ADC-EN ADC-AVG RESERVED TRIG-ADC TRIG ADC-DATA ADC-DATA ADC-DRDY Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 56 SRAM-CONFIG SRAM-ADDR SRAM-DATA SRAM-DATA BRDCAST-DATA BRDCAST-DATA The highlighted gray cells indicate the register bits or fields that are stored in the NVM. X = Don't care. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 57 Section 7.22 GENERAL-STATUS Section 7.23 CMP-STATUS Section 7.24 GPIO-CONFIG Section 7.25 DEVICE-MODE-CONFIG Section 7.26 INTERFACE-CONFIG Section 7.27 SRAM-CONFIG Section 7.28 SRAM-DATA Section 7.29 BRDCAST-DATA Section 7.30 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 58 Table 7-4. Access Type Codes Access Type Code Description Don't care Read Type Read Write Type Write Reset or Default Value Value after reset or the default value Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 59: Nop Register (Address = 00H) [Reset = 0000H]

    Data are in straight-binary format. MSB left aligned. Use the following bit alignment: AFE532A3W: {DAC-1-MARGIN-HIGH[9:0], X, X} AFE432A3W: {DAC-1-MARGIN-HIGH[7:0], X, X, X, X} X = Don't care bits. Don't care Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 60: Dac-2-Margin-High Register (Address = 01H) [Reset = 0000H]

    Data are in straight-binary format. MSB left aligned. Use the following bit alignment: {DAC-1-MARGIN-LOW[9:0], X, X} {DAC-1-MARGIN-LOW[7:0], X, X, X, X} X = Don't care bits. Don't care Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 61: Dac-2-Margin-Low Register (Address = 02H) [Reset = 0000H]

    011: Gain = 2 ×, internal reference. 100: Gain = 3 ×, internal reference. 101: Gain = 4 ×, internal reference. Others: Invalid. 000h Don't care Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 62: Dac-1-Gain-Cmp-Config Register (Address = 15H) [Reset = 0000H]

    Table 7-14. DAC-2-GAIN-CONFIG Register Field Descriptions Field Type Reset Description 15-13 Don't care 12-10 IOUT-GAIN 000: GAIN = 2/3. 001: GAIN = 1/2. Others: Invalid. 000h Don't care Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 63: Dac-1-Cmp-Mode-Config Register (Address = 17H) [Reset = 0000H]

    01: Hysteresis provided using DAC-1-MARGIN-HIGH and DAC-1- MARGIN-LOW registers. 10: Window comparator mode with DAC-1-MARGIN-HIGH and DAC-1-MARGIN-LOW registers setting window bounds. 11: Invalid. 000h Don't care Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 64: Dac-0-Func-Config Register (Address = 12H) [Reset = 0000H]

    0111: 60.72 µs/step 1000: 91.12 µs/step 1001: 136.72 µs/step 1010: 239.2 µs/step 1011: 418.64 µs/step 1100: 732.56 µs/step 1101: 1282 µs/step 1110: 2563.96 µs/step 1111: 5127.92 µs/step Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 65 000: 4 µs/step 001: 12 µs/step 010: 27.04 µs/step 011: 60.72 µs/step 100: 136.72 µs/step 101: 418.64 µs/step 110: 1282 µs/step 111: 5127.92 µs/step Don't care Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 66: Dac-1-Func-Config Register (Address = 18H) [Reset = 0000H]

    0111: 60.72 µs/step 1000: 91.12 µs/step 1001: 136.72 µs/step 1010: 239.2 µs/step 1011: 418.64 µs/step 1100: 732.56 µs/step 1101: 1282 µs/step 1110: 2563.96 µs/step 1111: 5127.92 µs/step Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 67 000: 4 µs/step 001: 12 µs/step 010: 27.04 µs/step 011: 60.72 µs/step 100: 136.72 µs/step 101: 418.64 µs/step 110: 1282 µs/step 111: 5127.92 µs/step Don't care Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 68: Dac-2-Func-Config Register (Address = 06H) [Reset = 0000H]

    0111: 60.72 µs/step 1000: 91.12 µs/step 1001: 136.72 µs/step 1010: 239.2 µs/step 1011: 418.64 µs/step 1100: 732.56 µs/step 1101: 1282 µs/step 1110: 2563.96 µs/step 1111: 5127.92 µs/step Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 69 000: 4 µs/step 001: 12 µs/step 010: 27.04 µs/step 011: 60.72 µs/step 100: 136.72 µs/step 101: 418.64 µs/step 110: 1282 µs/step 111: 5127.92 µs/step Don't care Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 70: Dac-0-Data Register (Address = 1Bh) [Reset = 0000H]

    Data are in straight-binary format. MSB left-aligned. Use the following bit-alignment: AFE532A3W: {DAC-2-DATA[9:0], X, X} AFE432A3W: {DAC-2-DATA[7:0], X, X, X, X} X = Don't care bits. Don't care Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 71: Adc-Config-Trig Register (Address = 1Dh) [Reset = 0000H]

    0: Default state after ADC is triggered. ADC data is invalid. 1: Default state when ADC is not triggered. The value 1 indicates ADC data is valid after the ADC is triggered. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 72: Common-Config Register (Address = 1Fh) [Reset = 0Fffh]

    11: Power-down DAC channel 0 with Hi-Z to AGND. RESERVED Always write Fh. DAC-PDN-2 00: Power-up DAC channel 2. Others: Power-down DAC channel 2 with 1.2 kΩ to AGND. RESERVED Always write 1h. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 73: Common-Trigger Register (Address = 20H) [Reset = 0000H]

    0: NVM write not triggered 1: NVM write triggered. This bit self-resets. NVM-RELOAD 0: NVM reload not triggered 1: Reload data from NVM to register map. This bit self-resets. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 74: Common-Dac-Trig Register (Address = 21H) [Reset = 0000H]

    1: Start function generation as per FUNC-GEN-CONFIG-x in the DAC-x-FUNC-CONFIG register. 15, 11-7 Don't care RESET-CMP-FLAG-1 0: Latching-comparator output unaffected 1: Reset latching-comparator and window-comparator output. This bit self-resets. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 75: General-Status Register (Address = 22H) [Reset = 20H, Device-Id, Version-Id]

    0: NVM is available for read and write. 1: NVM is not available for read or write. DEVICE-ID AFE532A3W: 01h Device identifier. AFE432A3W: 02h VERSION-ID Version identifier. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 76: Cmp-Status Register (Address = 23H) [Reset = 000Ch]

    7.25 GPIO-CONFIG Register (address = 24h) [reset = 0000h] Figure 7-25. GPIO-CONFIG Register GF-EN GPO-EN GPO-CONFIG GPI-CH-SEL GPI-CONFIG GPI-EN R/W-0h X-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 77 C or SPI and to the RESET field through I Others: Invalid GPI-EN 0: Disable input mode for GPIO/SDO pin. 1: Enable input mode for GPIO/SDO pin. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 78: Device-Mode-Config Register (Address = 25H) [Reset = 0000H]

    Always write 0. Don't care FSDO-EN 0: Fast SDO disabled 1: Fast SDO enabled Don't care SDO-EN 0: SDO disabled 1: SDO enabled on GPIO/SDO pin Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 79: Sram-Config Register (Address = 2Bh) [Reset = 0000H]

    AFE432A3W: {BROADCAST-DATA[7:0], X, X, X, X} X = Don't care bits. The BRD-CONFIG-X bit in the DAC-x-FUNC-CONFIG register must be enabled for the respective channels. Don't care. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 80: Application And Implementation

    A0/SDI SCL/SYNC 10 k ¢ HIGH BUFFER VOUT – GPIO/SDO 10 k £ BUFFER Output Configuration AFEx32A3W Logic AGND PGND Figure 8-1. Electro-Absorption Modulated Laser Biasing Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 81 AFEx32A3W with the selected gain applied. Select an op-amp that supports the output voltage range and output current drive required by the EAM. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback...
  • Page 82 WRITE ADC-CONFIG-TRIG(0x1D), 0x23, 0xC0 //Save settings to NVM WRITE COMMON-TRIGGER(0x20), 0x00, 0x02 //Use GPIO pin to power on/off IDAC //ADC trigger WRITE ADC-CONFIG-TRIG(0x1D), 0x23, 0xC1 //ADC readback READ ADC-DATA(0x1E) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 83: Power Supply Recommendations

    1.5 µF for the CAP pin. Note The AFEx32A3W do not provide automatic thermal shutdown. Therefore, the external circuit design must maintain the junction temperature within the specified limits. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: AFE532A3W AFE432A3W...
  • Page 84: Layout

    AFE532A3W, AFE432A3W A0/SDI LDO Bypass Capacitor PVDD Decoupling SDA/SCLK Capacitor IOUT PVDD Figure 8-5. Layout Example Note: The ground and power planes have been omitted for clarity. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE532A3W AFE432A3W...
  • Page 85: Device And Documentation Support

    All trademarks are the property of their respective owners. 9.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
  • Page 86 PACKAGE OPTION ADDENDUM www.ti.com 9-Dec-2023 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing Ball material (4/5) AFE432A3YBHR ACTIVE DSBGA 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 Samples...
  • Page 87 PACKAGE OPTION ADDENDUM www.ti.com 9-Dec-2023 Addendum-Page 2...
  • Page 88 PACKAGE MATERIALS INFORMATION www.ti.com 10-Dec-2023 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS B0 W Reel Diameter Cavity Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE...
  • Page 89 PACKAGE MATERIALS INFORMATION www.ti.com 10-Dec-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) *All dimensions are nominal Device Package Type Package Drawing Pins Length (mm) Width (mm) Height (mm) AFE432A3YBHR DSBGA 3000 182.0 182.0 20.0 AFE532A3YBHR DSBGA 3000 182.0 182.0 20.0 Pack Materials-Page 2...
  • Page 90 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2024, Texas Instruments Incorporated...

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