Dma Global Address Register Used For Split Address - Texas Instruments TMS320C6201 Reference Manual

5.8.2 Split Address Generation
Figure 5–11.DMA Global Address Register Used for Split Address
31
The above sequence is maintained for all transfers. However, the transmit
transfers do not have to wait for all previous receive element transfers to finish
before proceeding. Therefore, it is possible for the transmit stream to get
ahead of the receive stream. The DMA channel transfer counter decrements
(or reinitialize) after the associated transmit transfer finishes. However, re-
initialization of the source address register occurs after all transmit element
transfers finish. This configuration works as long as transmit transfers do not
eight or more transfers ahead of the receive transfers. If the transmit transfers
do get ahead of the receive transfers, transmit element transfers are stopped,
possibly causing synchronization events to be missed. For cases in which
receive or transmit element transfers are within seven or less transfers of the
other, the DMA channel maintains this information as internal status.
The DMA global address register selected by the SPLIT field in the DMA pri-
mary control register determines the address of the peripheral that is to be ac-
cessed for split transfer:
Split source address: This address is the source for the input stream to the
'C6000. The selected DMA global address register contains this split
source address.
Split destination address: This address is the destination for the output
data stream from the 'C6000. The split destination address is assumed to
be one word address (four byte addresses) greater than the split source
address.
SPLIT ADDRESS
RW, +0
The two LSBs are fixed at 0 to force alignment at a word address. The third LSB
is 0 because the split source address is assumed to be on an even word bound-
ary. Thus, the split destination address is assumed to be on an odd word bound-
ary. These relationships hold regardless of the width of the transfer. For external
peripherals, you must design address decoding appropriately to adhere to this
convention.
Direct Memory Access (DMA) Controller
Split-Channel Operation
3 2 0
Reserved
R, +0
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