Texas Instruments PGA411-Q1 Instruction Manual

Texas Instruments PGA411-Q1 Instruction Manual

Resolver sensor interface
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1 Features

Qualified for Automotive Applications
1
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
Resolver-to-Digital Converter (RDC)
Exciter Preamplifier and Power Amplifier
Exciter-Boost Power Supply With Spread
Spectrum
Analog Front-End
Automatic Offset Calibration
Type-II PI Controller Tracking Loop
Parallel, Encoder, or SPI Data Output
Analog Data Output
SafeTI™ Semiconductor Component
– Designed for Functional Safety Applications
– Developed According to the Requirements of
ISO 26262
Automatic and Manual Phase Correction
Sensor-Input Fault Detection
Diagnostics Interrupt Output
Internal and External Oscillator
Analog and Logic Built-In Self-Test for Fault
Detection
64-Pin HTQFP PowerPAD™ IC Package

2 Applications

Motor Control
HEV/EV Motor Inverters
Electrical Power Steering
Integrated Start-Stop Generators
Servo Drives
AC Drives
Industrial Robots
CNC Machinery
Elevators and Lifts
Injection Molding Machinery
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Order
Product
Technical
Folder
Now
Documents
PGA411-Q1 Resolver Sensor Interface
Support &
Tools &
Community
Software
SLASE76E – NOVEMBER 2015 – REVISED AUGUST 2017

3 Description

The PGA411-Q1 device is a resolver-to-digital
converter, with an integrated exciter-amplifier and
boost-regulator power supply, that is capable of both
exciting and reading the sine and cosine angle from a
resolver sensor. The integration of the exciter
amplifier and boost supply with protection in the
PGA411-Q1 device enables cost reductions of the bill
of materials (BOM) and space reductions on the
printed-circuit board (PCB) because of the elimination
of most external and passive components.
The PGA411-Q1 device also has an internal clock for
generating a sine wave used for sensor excitation.
The architecture of the analog front-end (AFE) allows
the user to output 10 bits or 12 bits of resolution for
the angle position and velocity. Because of high
integration, the PGA411-Q1 device has diagnostics
and protection on each internal block inside the
device. The integrated diagnostics monitor can signal
a fault condition through a dedicated pin which can
be used as a MCU interrupt. These features allow
flexibility in both resolver sensor choice and platform
scalability.
Additionally,
designed according to the requirements of ISO 26262
for functional safety applications.
Device Information
PART
PACKAGE
NUMBER
PGA411-Q1
HTQFP (64)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified System Diagram
Resolver Sensor
Resolver to Digital Interface
&
SIN
PGA411-Q1
COS
EXC
Copyright © 2016, Texas Instruments Incorporated
PGA411-Q1
the
PGA411-Q1
was
(1)
BODY SIZE (NOM)
10.00 mm × 10.00 mm
System Control
MCU
I/O

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Summary of Contents for Texas Instruments PGA411-Q1

  • Page 1: Features

    Resolver-to-Digital Converter (RDC) of most external and passive components. • Exciter Preamplifier and Power Amplifier The PGA411-Q1 device also has an internal clock for generating a sine wave used for sensor excitation. • Exciter-Boost Power Supply With Spread The architecture of the analog front-end (AFE) allows...
  • Page 2: Table Of Contents

    Removed the ENFLOOPE option from the data sheet ......................• Updated DEV_CONFIG1 data split info in Table 7 ......................• Updated register description for Bit 4-3 ..........................• Updated Table 41 Table 42............................Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 3 • Added the resistor to ground production statement in the Analog Output section and Pin Functions table and added the resistor to the PGA411-Q1 Typical Application Diagram image ................... • Changed the factory setting from 003Fh (00111111b) to 00CEh (11001110b) for the DEV_CLCRC register in the User EEPROM Space SPI Mapping table and in the DEV_CLCRC Register section............
  • Page 4: Pin Configuration And Functions

    Negative input to the AFE from the resolver exciter coil INHB Input Inhibit function and output data hold (1) I = input; O = output; I/O = input and output; P = power Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 5 SCLK Input SPI clock Input SPI data input Output SPI data output Test input and output (I/O). Texas Instruments reserved pin. Connect this pin to TEST — ground. Input Data output select 0 for angle and velocity Input Data output select 1 for angle and velocity —...
  • Page 6: Specifications

    2.97 3.63 I/O supply input = 5 V 5.25 Differential IZ1, IZ2, IZ3, ); (V amplitude input Operating fee-air temperature –40 °C Operating junction temperature –40 °C Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 7: Thermal Information

    ≥ 7 V; EXTPS CCSW nBOOST_FF = 1 Exciter power-supply With 10% spread spectrum EXTPS switching frequency Exciter power-supply µH EXCPS inductor range Exciter power-supply µF EXCPS capacitor range Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 8: Exciter Output, Amplifier, And Power Supply

    2.25 2.295 COMAFE = 2.5 V; GAINCOS = GAINSIN = 0x03 3.43 3.57 IZx input voltage range (pk- = 0.75; C = 0.75 COMAFE=2.5 V GAIN GAIN Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 9: Digital Tracking Loop Characteristics

    µs VDDOVUV undervoltage deglitch time = 4.75 to 5.25 V; SPI flag; Maximum current draw from V current limit VDDLIM for external consumption is 10 mA Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 10 62.4 67.6 OSIN, OCOS pins; Reported by SPI flags; OSHORTH = 0x6 64.8 67.5 70.2 OSIN, OCOS pins; Reported by SPI flags; OSHORTH = 0x7 67.2 72.8 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 11 IZ1, IZ2, IZ3, IZ4 pins; V = 5 V; This threshold is a percentage 3.42 3.65 3.81 of V ; Reported by SPI flags; DVMSENH = 0x7 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 12: Regulator Characteristics

    LOAD Internal pullup resistance FAULT pin; V = 0 V kΩ PUOD LOGIC INPUT High logic-level input threshold Low logic-level input threshold (1) Parameter specified by design. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 13: Oscillator Characteristics

    Propagation delay from rising edge of SCLK to SDO = 50 pF pd_so SPI transfer inactive time (time between two transfers) during which NCS must remain high w_cs Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 14: Timing Diagrams

    Wait 100 ms Approx. 100 ms Approx. 100 ms 2.3 ms 2.3 ms Data Update Data Update Data Update [12:0] 100 ns Figure 2. Power-Up Timing Diagram Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 15: Typical Characteristics

    Time (ms) Time (ms) D005 D006 AMODE = 0 AMODE = 0 Figure 7. 10° Step Response in 12-Bit Mode Figure 8. 180° Step Response in 12-Bit Mode Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 16 Time (ms) Time (ms) D007 D008 AMODE = 1 AMODE = 1 Figure 9. 10° Step Response in 12-Bit Mode Figure 10. 180° Step Response in 12-Bit Mode Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 17: Functional Block Diagram

    7 Detailed Description 7.1 Overview The PGA411-Q1 device is a resolver sensor interface device with an integrated exciter amplifier and boost power supply. The PGA411-Q1 device is capable of running with either 10-bit or 12-bit resolution. The internal boost power supply for the exciter can be used from 10 V to 17 V which enables the exciter output to be adjustable...
  • Page 18: Feature Description

    7.3.1 Exciter Amplifier Power Supply The exciter power supply implemented in the PGA411-Q1 device is supplied by the VCCSW pin for the internal driver logic and error correction and the VSW pin as a switch pin for creating a higher voltage rail. Both of these...
  • Page 19: Rms

    DEV_PHASE_CFG register. These bits are also the main enable control for the full exciter signal generation path. When the EXTMODE bit is set to 00 or 11, the exciter signal path is disabled causing the PGA411-Q1 device to signal a FAULT condition. The exciter preamplifier offers the ability to adjust the exciter output signal to compensate for the variations of the transfer ratio for the resolver sensor.
  • Page 20: Added Content To The Exciter Signal Preamplifier Section

    For signal monitoring or different exciter topologies, the output signal from the exciter preamplifier is available at the ORS pin of the PGA411-Q1 device. The output voltage is referenced to the voltage on the COMAFE pin. An external power amplifier such as the ALM2402-Q1 can be connected to the ORS pin to drive very high current sensors.
  • Page 21: Updated Figure 14 And Added Table 1

    7.3.3 Analog Front-End The AFE in the PGA411-Q1 device together with the tracking loop, performs the resolver-to-digital converter (RDC) functionality. The AFE block connects to the SIN and COS coils of the resolver sensor where the SIN (IZ2 and IZ4) and the COS (IZ1 and IZ3) signals are amplified by differential input amplifiers with variable gain.
  • Page 22 For external signal monitoring, the PGA411-Q1 device outputs the amplified SIN and COS signals at the dedicated OSIN and OCOS pins. These output pins are referenced to the COMAFE pin.
  • Page 23 PGA411-Q1 device. While in analog form, the input SIN and COS signals are multiplied with feedback SIN and COS from the digital tracking loop. When the multiplied signals are subtracted, a control deviation voltage signal, VΦ...
  • Page 24 PULSE K × cos, × sin&t COMAFE OCOS cos- From AFE To Digital Tracking Loop sin- From Digital Control Copyright © 2016, Texas Instruments Incorporated Figure 16. Analog Multiply and Subtract BMODE OHYS ™ œ Angle PULSE Output 12 / 10...
  • Page 25 The output data is formatted for proper output inside the accumulator. The output resolution of the PGA411-Q1 device is also selected through the BMODE0 pin. When the BMODE0 pin is low (DGND) the device operates in 10-bit mode.
  • Page 26: Added New Content To The Automatic Offset Correction Section

    It is important to minimize the offset introduced by the analog front-end for the tracking loop to report angle with minimum error. The PGA411-Q1 device therefore implements an initial automatic offset correction and a real- time automatic offset correction routines to remove offset in the AFE and tracking loop.
  • Page 27 Value Sweep Control Copyright © 2016, Texas Instruments Incorporated Figure 19. Amplifier Automatic Offset Calibration The fault flag, FAFECAL in the DEV_STAT7 register indicates when the calibration encounters an error. In this case, the AFE offset correction procedure will be attempted again in 100 ms. If the next calibration procedure ends correctly, then the FAFECAL fault will be cleared.
  • Page 28: Updated Figure 20

    SIN or COS input signals. If this phase shift is too large, it can lead to tracking loop instability and wrong angle data of the resolver-to-digital converter. The PGA411-Q1 implements a phase offset correction circuit to correct the position of the reference pulse while eliminating the phase mismatch.
  • Page 29 Phase Offset Correction From AFE From Multiply Copyright © 2016, Texas Instruments Incorporated Figure 21. PGA411-Q1 Phase Offset Correction The phase-offset correction circuit has two modes of operation: auto-mode phase delay and manual-mode phase delay. Table 2 lists the PDEN and APEN bit values (DEV_PHASE_CFG) for selecting each of these modes.
  • Page 30 7.3.6.3.1 Analog Front-End (AFE) Diagnostics The AFE diagnostic monitor tracks signals that are fed into the PGA411-Q1 device from the resolver sensor SIN and COS coils. This tracking occurs by monitoring the IZx (where x = 1 through 4) signals and the OSIN output used to monitor the SIN-coil (IZ2 through IZ4) faults as well as OCOS output used to monitor the COS-coil (IZ1 through IZ3) faults.
  • Page 31 OVIZL From AFE From AFE Stage 1 Stage 2 Copyright © 2016, Texas Instruments Incorporated Figure 22. Open Input, Short Input, Input Fault, and Loop Stability Diagnostics Implementation In addition to Figure Figure 23 shows the same four diagnostics along with the SPI-adjustable threshold levels of each.
  • Page 32 TOPEN bits in the DEV_OVUV5 register. The fault flags for the open input diagnostic are FOSINOPH, FOSINOPL, FOCOSOPH, and FOCOSOPL in the DEV_STAT1 register. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 33 1.35 V DVMSENL SPI Adjustable Limit Fixed Copyright © 2016, Texas Instruments Incorporated Figure 24. Signal Integrity Check Implementation and SPI Adjustable Thresholds 7.3.6.3.1.6 Exciter Monitor The diagnostic employs the exciter monitor circuit that is described in the Analog Front-End section to track the duty cycle of the exciter reference pulse.
  • Page 34 Reference Pulse FEXTMONH Reference Pulse Figure 25. Exciter Monitor High and Low Diagnostics 7.3.6.3.2 Exciter Amplifier Diagnostics The PGA411-Q1 exciter amplifier implements the following diagnostics: • Single-ended overvoltage output • Differential output undervoltage and overvoltage • Excited output current limit 7.3.6.3.2.1 Single-Ended Overvoltage Output...
  • Page 35: Removed Content From The Exciter-Output Current Limit Section

    DEV_PHASE_CFG register. Because the exciter output topology is a bridge-tied load drive, the two independent amplifiers monitor for undervoltage at the respective outputs. The default PGA411-Q1 configuration for reporting the differential undervoltage mode reporting the fault if either of these outputs detects undervoltage (logical OR).
  • Page 36 Figure 29. PGA411-Q1 Thermal Protection 7.3.7 Clock Generation The PGA411-Q1 device can generate a digital system clock through an internal oscillator or an external crystal oscillator. The system clock is generated by setting the state of the ECLKSEL pin low (GND) to select the internal 20-MHz oscillator, or high (V ) to select the external oscillator.
  • Page 37 SELFEXT bits, determines the exciter frequency. 7.3.7.1 Loss-of-Clock Monitor When the ECLKSEL pin on the PGA411-Q1 device is set high (which means the main system clock is referenced to an external clock generated by a crystal or resonator element) the internally generated clock is used to monitor for correct operation of the device system clock.
  • Page 38: Added Image And New Content To The Digital Parallel Output Section

    7.3.9 Digital Input and Output All digital I/O pins in PGA411-Q1 device are referenced to the VIO input pin. The PGA411-Q1 device supports digital voltage levels between 3.3 V and 5 V. The following PGA411-Q1 pins are considered digital I/O pins: OUTA, OUTB, ECLKSEL, BMODE0, TEST, NRESET, INHB, FAULTRES, PRD, FAULT, NCS, SCLK, SDI, SDO, AMODE, OMODE, VA0, VA1, ORD[11:0], and OUTZ.
  • Page 39 Velocity output at ORD[11:0] The INHB pin controls the update of the data output for the PGA411-Q1 device. When the INHB pin is high (VIO), the output data is sampled at the ORD[11:0] pins as soon as the data is available. When the INHB pin is set low (DGND), the data output at theORD[11:0] pins is held at the last sampled output.
  • Page 40: Added New Content To The Ord Clock Section

    ORDCLK in combination with the angle or velocity data available on ORD[12:0]. Clock off because of low inhibit 100 ns 25 ns pin, or disabled tracking loop ORDCLK ORD[12:0] Figure 34. ORD Timing Characteristics Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 41 The corresponding locations are the ORDANGLE bit in the DEV_STAT5 register for angle data value and the ORDVELOCITY bit in the DEV_STAT6 register for velocity data value. Use the following equations to convert the PGA411-Q1 parallel output or SPI data into meaningful angle and velocity values: •...
  • Page 42 NPLE bits in the DEV_CONFIG1 register. For this case, use Equation 15 to calculate the emulated angle step. (degrees) 12 NPLE (15) The PGA411-Q1 device supports pole section up to 4x. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 43 7.3.11 Fault Reporting Fault Reporting in the PGA411-Q1 device is signaled through the FAULT pin and SFAULT SPI register. The FAULT pin is an open-drain output structure. The pin is LOW when no fault is reported. The pin is in Hi-Z state when a fault is present in the system.
  • Page 44: Removed The Enfloope Option From The Data Sheet

    Optionally, masking some faults that can signal a fault condition in the system is possible. By doing so, the PGA411-Q1 device reports the fault through the assigned SPI fault flag however no action occurs as long as the mask is set.
  • Page 45: Device Functional Modes

    In the system, the NRESET pin asserts the nPOR in the device logic. When the NRESET pin is low (DGND), the PGA411-Q1 logic is frozen and the device is in the RESET state. When the NRESET pin is pulled up, the logic is enabled after a 70-µs deglitch period and the device is operational.
  • Page 46 AFE, V regulator, and oscillator. The state of the FAULT pin is low. During active device operation in any state the PGA411-Q1 device can cause an internal reset because of the following: •...
  • Page 47 7.4.4 FAULT State A device fault is indicated by setting the FAULT pin in the Hi-Z state in which case the PGA411-Q1 device is in the FAULT state. While in this state, the digital tracking loop is disabled and no angle or velocity data is updated at the output if the device.
  • Page 48 7.4.5 EEPROM Memory The EEPROM memory space in the PGA411-Q1 device is split into two functional blocks: a User EEPROM space and a reserved, Texas Instruments internal-use EEPROM space used for device trim and manufacturing data values. The user EEPROM-memory space is directly accessed through the SPI registers.
  • Page 49 + X + 1 with an initial seed of 0xFF and MSB ordering) and is performed on a 136-bit concatenated string, byte- wise beginning with the least-significant byte. To optimize implementation, the PGA411-Q1 device splits the registers into 8-bit chunks for the CRC calculation which are then ordered from most-significant bit to least- significant bit.
  • Page 50: Updated Dev_Config1 Data Split Info In Table 7

    The voltage signals are unchanged during the analog BIST process on the implemented comparators and therefore no real undervoltage or overvoltage occurs in the system because of the BIST. See Figure Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 51 In parallel to the analog BIST, the logical BIST runs stuck-at-fault patterns for logical integrity checking. The analog and logical BISTs automatically occur whenever the PGA411-Q1 device is in the DIAGNOSTICS state. The result of the analog BIST is monitored on the ABISTF bit while the result of the logic BIST fault is monitored by the LBISTF bit in the DEV_STAT4 register.
  • Page 52 5:0 [LSB] The following procedure lists steps for a successful configuration CRC calculation: 1. The MCU writes the desired data to the configuration and control registers when the PGA411-Q1 device is in the DIAGNOSTICS state. If the DEV_CONTROL1 and DEV_CONTROL2 registers are updated with new data, the device requires unlocking by entering a SPI unlock sequence in the DEV_UNLK_CTRL1 register.
  • Page 53 ORD11 through ORD0 pins and the PRD pin are reported by the SORD and SPRD bits in the DEV_STAT2 register. The output signal monitor is configured in a way that the PGA411-Q1 device does act when a signal mismatch occurs. The only exception to this rule is when the FAULT pin monitor detects an output mismatch. The FAULT...
  • Page 54: Programming

    NCS pin must remain high is 200 ns. The PGA411-Q1 device SPI response frame is always one SPI transfer behind the SPI master frame. NOTE Upon receiving a SPI read of the angle or velocity data, the PGA411-Q1 device goes through 1 to 2 clock cycles to load the angle or velocity data into the SPI to send out.
  • Page 55 Table 11 lists a set of SPI CRC examples. Table 11. SPI CRC Examples 24-BIT SPI FRAME CRC-6 0xAE0000 0x11 0x950055 0x22 0x855555 0x29 0x0D2FFE 0x0D 0x85FFFF 0x38 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 56 2. Write 0x0055 to DEV_EE_CTRL4 3. Write 0x00AA to DEV_EE_CTRL4 4. Write 0x00F0 to DEV_EE_CTRL4 In each case the full length of the sequence write time cannot exceed 10 ms. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 57 SLASE76E – NOVEMBER 2015 – REVISED AUGUST 2017 7.6 Register Maps 7.6.1 SPI Register Map Layout Configuration Table 5 provides an overview of each register located in the PGA411-Q1 SPI memory map. For more details refer to the corresponding REGMAP register (see Table 13).
  • Page 58 DEV_OVUV1 DEV_OVUV2 DEV_OVUV3 DEV_OVUV4 DEV_OVUV5 DEV_OVUV6 DEV_TLOOP_CFG DEV_AFE_CFG DEV_PHASE_CFG DEV_CONFIG1 DEV_CONTROL1 DEV_CONTROL2 DEV_CONTROL3 DEV_STAT1 DEV_STAT2 DEV_STAT3 DEV_STAT4 DEV_STAT5 DEV_STAT6 DEV_STAT7 DEV_CLCRC DEV_CRC CRCCALC DEV_EE_CTRL1 DEV_CRC_CTRL1 DEV_EE_CTRL4 DEV_UNLK_CTRL1 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 59 000 -140 mA 001 -150 mA 010 -165 mA 011 -180 mA 100 -200 mA 101 -230 mA 110 -550 mA (not recommended) 111 -550 mA (not recommended) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 60 × 0.575 V 011: V × 0.6 V 100: V × 0.625 V 101: V × 0.65 V 110: V × 0.675 V 111: V × 0.7 V Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 61 IZx Input Integrity Check Low Threshold level select: 000: 2.4 V 001: 2.25 V 010: 2.1 V 011: 1.95 V 100: 1.8 V 101: 1.65 V 110: 1.5 V 111: 1.35 V Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 62 IZx Input Overvoltage High Threshold level select: 00: V × 0.75 V 01: V × 0.8 V 10: V × 0.85 V 11: V × 0.9 V Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 63 × 0.8 V 011: V × 0.825 V 100: V × 0.85 V 101: V × 0.875 V 110: V × 0.9 V 111: V × 0.925 V Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 64: Updated Register Description For Bit 4-3

    Standard Auto Phase configuration VEXT_CFG VEXT Configuration bit: set to 1 when the VEXT supply is used for an external exciter amplifier. Set to 0 allow normal boost VEXT monitoring. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 65 OSIN/OCOS Open Circuit Deglitch Select: 000: 35 µs 001: 50 µs 010: 65 µs 011: 80 µs 100: 95 µs 101: 110 µs 110: 125 µs 111: 140 µs RESERVED 000000000 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 66 01: 0.2 V 10: 0.25 V 11: 0.8 V LPETHH Tracking Loop Error High Threshold level select: 00: 0.1 V 01: 0.2 V 10: 0.25 V 11: 0.8 V Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 67 1x: DO NOT USE (may result in angle errors at low rotation speed) SENCLK Exciter Clock input Select: 0: Exciter Clock is Referenced to system Clock 1: Not recommended - exciter may not function Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 68 000h GAINCOS COS Input AFE Gain: 00: 0.75 01: 1 10: 2.25 11: 3.50 GAINSIN SIN Input AFE Gain: 00: 0.75 01: 1 10: 2.25 11: 3.50 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 69 0111: 1.3 V 1000: 1.2 V 1001: 1.1 V 1010: 1.0 V 1011: 0.9 V 1100: 0.8 V 1101: 0.7 V 1110: 0.6 V 1111: 0.5 V Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 70 Exciter Power Supply Voltage Output Select: 000: 10 V 001: 11 V 010: 12 V 011: 13 V 100: 14 V 101: 15 V 110: 16 V 111: 17 V Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 71 1: Enabled MIZOV Mask Input IZ1, IZ2, IZ3, IZ4 Overvoltage (FIZH) 0: Disabled 1: Enabled MIZUV Mask Input IZ1, IZ2, IZ3, IZ4 Undervoltage (FIZL) 0: Disabled 1: Enabled Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 72 NORMAL This bit is self-clearing; reading always returns a zero value. This bit can always be written, i.e., it is not write-access protected. A zero-value is used for this bit in the device CRC calculation. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 73 ENEXTUV Exciter Undervoltage Fault Enable Control: 0: The Exciter is Disabled on a detected EXTUV fault 1: The Exciter will Remain Enabled when a fault is detected Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 74 This control is set to 0 when an un-masked fault (see the Exciter Output, Amplifier, and Power Supply Characteristics table) becomes active. This state is maintained as long as the fault remains active. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 75 This bit will clear on read. FGOPEN Ground Open Fault. This bit will clear on read. FOSHORT Input IZ1, IZ2, IZ3, IZ4 Short Fault. This bit will clear on read. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 76 R-0b R-0b SORD R-0b Table 28. DEV_STAT2 Register Field Descriptions FIELD TYPE FACTORY DESCRIPTION SETTINGS RESERVED SPRD PRD pin Signal Monitor 13-0 SORD ORD[13:0] pin Signal Monitor Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 77 OVIZL selected reference. This bit will clear on read. FIZH4 Input IZ4 High Overvoltage Fault IZ4 voltage level is checked against the OVIZH selected reference. This bit will clear on read. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 78 Digital Input / Output pin Missmatch Fault. This bit will clear on read. SFAULT FAULT pin Signal Monitor SOUTA OUTA pin Signal Monitor SOUTB OUTB pin Signal Monitor SOUTZ OUTZ pin Signal Monitor Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 79 Angle Position Output Value (Right Justified). Angle values are stored in unsigned 2's complement format. ORD12 is always 0. ORD11 and ORD10 will be 0 if the PGA411-Q1 is in 10-bit mode. 7.6.2.19 DEV_STAT6 Register (Offset = 12h) [Factory Settings = 0000h]...
  • Page 80 Figure 63. DEV_CLCRC Register RESERVED R-0b ECCRC R/W-11001110b Table 34. DEV_CLCRC Register Field Descriptions FIELD TYPE FACTORY DESCRIPTION SETTINGS 15-8 RESERVED ECCRC 11001110b User EEPROM Space CRC value Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 81 Table 36. CRCCALC Register Field Descriptions FIELD TYPE FACTORY DESCRIPTION SETTINGS 15-8 RESERVED CRCRC Device Registers data Calculated CRC to be compared against expected CRC value in DEV_CRC Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 82 SETTINGS 15-1 RESERVED CRCCTL CRC Check Sequence Control: 0: Single CRC check is selected 1: Contiguous CRC check is selected (CRC check is performed every 2 ms) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 83 Device Control Registers Unlock Sequence. The following sequence unlocks DEV_CONTROL1 and DEV_CONTROL2 registers: 1. 0x0F 2. 0x55 3. 0xAA 4. 0xF0 Must be completed within 10 ms. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 84 (EPS), and Start-Stop Generators typically use resolver sensors. 8.2 Typical Application The typical application is when the PGA411-Q1 device delivers an excitation output signal using the OE1 and OE2 pins and receives sine and cosine feedback from the IZ1 through IZ4 pins. There are several external components, such as a crystal oscillator, inductor, diodes, and capacitors that are also required in this application.
  • Page 85 NOTE: The maximum current allowed on digital pins such as NRESET and FAULT is 10 mA. Use pullup resistors as needed (the recommended value is 4.7 kΩ). Figure 70. PGA411-Q1 Typical Application Diagram Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 86: Updated Table 41 And Table 42

    The key specifications of any resolver sensor are the excitation voltage, frequency, impedance, and transformation ratio. These factors must be considered while designing with the PGA411-Q1 device. These parameters are typically specified in the data sheet for each resolver sensor; for this example, the sensor has an...
  • Page 87 50 Ω to as high as 200 Ω where the reactive inductive component varies with the frequency of operation. The PGA411-Q1 exciter signal output can be programmed from 10 kHz to 20 kHz. The excitation voltage can be programmed to be either 4 V or 7 V .
  • Page 88 A = 0.75 ± 3.5 = 1000pF =49.9NŸ = 1000pF OCOS Outside PGA411-Q1 Inside PGA411-Q1 Copyright © 2016, Texas Instruments Incorporated Gain setting resistors Input capacitor and R Open fault resistors Common-mode capacitors Figure 71. Selection of External Components for Filtering the IZx pins As previously described, the AFE gain can be selected between 0.75 and 3.5 which internally changes the R...
  • Page 89 Therefore an optimum value must be derived to keep the phase shift in the PGA411-Q1 correction range. The differential peak-to-peak signal (SIN, COS) of the PGA411-Q1 input must be from 0.188 V to 3 V as well. The resistance values for R and R are selected as 30 kΩ...
  • Page 90 = 64.2 NŸ = 40.2 NŸ EXTMODE = 92.4 NŸ Copyright © 2016, Texas Instruments Incorporated Figure 73. Exciter Output Gain Equation 22 to calculate the value of the variable-gain preamplifier (which is already calculated and selected through the EXTOUT_GL parameter).
  • Page 91 PGA411-Q1 www.ti.com SLASE76E – NOVEMBER 2015 – REVISED AUGUST 2017 8.2.4 Application Curves VSW = Boost switching node of PGA411-Q1 QVCC = Quiet VCC for PGA411-Q1 VEXTS= Exciter boost feedback and diagnostics VEXT = Exciter power supply inputs for fault monitoring...
  • Page 92 Input port connected to a timer, counter, capture, or compare module TIMER_O Output port connected to a timer, counter, capture, or compare module Data bus Control interface Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 93 ORD0 / OUT U TIMER_I OUTA TIMER_I OUTB TIMER_I OUTZ INHB GP_O / TIMER_O GP_O GP_O OMODE Copyright © 2016, Texas Instruments Incorporated Figure 82. Single PGA411-Q1 Parallel Data Output Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 94 TIMER_I OUTB TIMER_I OUTZ INHB GP_O / TIMER_O GP_O GP_O OMODE Copyright © 2016, Texas Instruments Incorporated (1) Optional Figure 83. Single PGA411-Q1 Emulated Encoder Data Output Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 95 The NRESET pin should remain on during normal operation of the circuit. 9 Power Supply Recommendations The PGA411-Q1 device has three ground pins which are for the power ground (PGND), digital ground (DGND), and quiet ground (QGND). NOTE The PGND and DGND pins are connected inside the PGA411-Q1 device.
  • Page 96: Sequencing Vio And Vcc

    The VCCSW pin is the input to the boost circuit. Typically, the VCCSW pin can be supplied with 5 V which means it can be tied with the other input supply rails of the PGA411-Q1 device. In high-current applications or applications that require the boost output to be greater than 14 V, a higher supply voltage may be required.
  • Page 97 PGA411-Q1 www.ti.com SLASE76E – NOVEMBER 2015 – REVISED AUGUST 2017 Layout Example (continued) Figure 86. Analog Front-End Layout Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 98 PGA411-Q1 SLASE76E – NOVEMBER 2015 – REVISED AUGUST 2017 www.ti.com Layout Example (continued) Figure 87. Decoupling Capacitors Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: PGA411-Q1...
  • Page 99: Device And Documentation Support

    (SLOS912) • PGA411-Q1 EVM User's Guide (SLAU658) • PGA411-Q1 PCB Design Guidelines (SLAA697) • PGA411-Q1 Step-by-Step Initialization With Any Host System (SLAA688) • Safety Manual for PGA411-Q1 Resolver Sensor Interface (SLAA684) • Troubleshooting Guide for PGA411-Q1 (SLAA687) 11.2 Community Resource The following links connect to TI community resources.
  • Page 100 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing Ball material (4/5) PGA411QPAPRQ1 ACTIVE HTQFP 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 PGA411QPAPRQ1...
  • Page 101 PACKAGE MATERIALS INFORMATION www.ti.com 30-Oct-2019 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Reel Reel Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) PGA411QPAPRQ1 HTQFP 1000 330.0 24.4 13.0 13.0 16.0 24.0 Pack Materials-Page 1...
  • Page 102 PACKAGE MATERIALS INFORMATION www.ti.com 30-Oct-2019 *All dimensions are nominal Device Package Type Package Drawing Pins Length (mm) Width (mm) Height (mm) PGA411QPAPRQ1 HTQFP 1000 350.0 350.0 43.0 Pack Materials-Page 2...
  • Page 103 GENERIC PACKAGE VIEW PAP 64 HTQFP - 1.2 mm max height QUAD FLATPACK 10 x 10, 0.5 mm pitch This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4226442/A www.ti.com...
  • Page 104 THERMAL PAD 4225982/A 08/2020 NOTES: PowerPAD is a trademark of Texas Instruments All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. This drawing is subject to change without notice.
  • Page 105 Solder mask tolerances between and around signal pads can vary based on board fabrication site. This package is designed to be soldered to a thermal pad on the board. Refer to technical brief, PowerPAD Thermally Enhanced Package, Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004). www.ti.com...
  • Page 106 EXAMPLE STENCIL DESIGN PAP0064N HTQFP - 1.2 mm max height PLASTIC QUAD FLATPACK 5.3) SEE TABLE FOR BASED ON DIFFERENT OPENINGS 0.1 THICK STENCIL FOR OTHER STENCIL THICKNESSES 64X (1.5) 64X (0.3) SYMM (11.4) 60X (0.5) METAL COVERED BY SOLDER MASK SYMM (11.4) SOLDER PASTE EXAMPLE...
  • Page 107 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated...

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