Latching Of The Boot Modes; Watchdog Timer; Peripherals; Selecting Peripherals Across Functional Domains - Texas Instruments AM62A7 Hardware Design Manual

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In case an ANDing logic is not used and the processor reset status output is used directly to reset the attach
devices, ensure the I/O levels of the attach device match the processor I/O level or use a level translator to
match the levels.
A controlled power switch is recommended to reset the SD Card since power cycling the SD Card is the only
way to reset the card to its default state. The 3.3 V power supply for the SD Card needs to be connected through
the controlled external power switch.
For more information, see the

6.2 Latching of the Boot Modes

For more details about the processor boot mode options, see
Boot modes and certain device configuration selections are latched at the rising edge of PORz_OUT. The
configuration and boot mode inputs are multiplexed with pins having GPIO or other functions. After the status
(level) on these pins are latched into the configuration registers, these pins are available to be used for their
primary function. The PORz_OUT pin indicates latching of boot mode configuration.

6.3 Watchdog Timer

Consider using external or internal watchdog timer based on the application requirement.

7 Peripherals

This section covers the device peripherals and modules, and is intended to be used in addition to the information
provided in the device-specific data sheet, TRM, and relevant Application Notes. The three types of documents
should be used as follows:
• Data Sheet: AC Timings, Guidance on pin functions, Pin mapping
• TRM: Functional Description, Programming Guide, Register offsets
• Application Notes: System-level understanding and issues

7.1 Selecting Peripherals Across Functional Domains

The processor is partitioned into three functional domains, each containing specific processing cores and
peripherals:
• MAIN domain
• Microcontroller (MCU) domain
• Wake-up (WKUP) domain
For most use cases, peripherals from any of the domain can be used. All peripherals, regardless of their domain,
are memory mapped, and the Arm
WKUP domains.

7.2 Memory

DDR Subsystem currently supports LPDDR4. For more information, see the device-specific data sheet and
TRM for data bus width (32-Bit), inline ECC support, speed (up-to 3733 MT/s) and Max addressable range (16
GBytes) selection.
The allowed configurations are 1 X 32-bit or 1 X 16-bit. 1 X 8-bit configuration is not a valid configuration.
Based on the application requirement, same memory device can be used with the AM625/AM623 and AM62A7/
AM62A3 devices due to the availability of 1 X 16-bit configuration.
When the AM62A7/AM62A3 devices are configured for 16-bit configuration, follow the DQS2..3 and other
termination recommendations shown in the 16-Bit, Single Rank LPDDR4 Implementation example of the
AM62Ax DDR Board Design and Layout
For more details, see the DDR Subsystem (DDRSS) section in the Memory Controllers chapter of the device-
specific TRM.
7.2.1 Processor DDR Subsystem and Device Register Configuration
The DDR controller and PHY have a large amount of parameters to configure, so to facilitate the configuration,
an online tool (SysConfig tool)
SPRAD85 – MARCH 2023
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Starter Kit SK-AM62A-LP EVM
® Cortex ® -A53 cores can see and access all peripherals in the MCU and
Guidelines.
is provided that generates an output file that is consumed by the driver.
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Device Configurations and Initialization
schematic.
Section 2.2.
Hardware Design Guide for AM62A7/AM62A3 Devices 9