Data Memory Access - Texas Instruments TMS320C6201 Reference Manual

Data Memory Access

2.5 Data Memory Access
2-8
The data memory controller services all CPU and DMA controller data re-
quests to internal data memory. Figure 2–4, Figure 2–5, and Figure 2–6 show
the directions of data flow and the master (requester) and slave (resource)
relationships between the modules:
The CPU requests data reads and writes to:
J
Internal data memory
J
On-chip peripherals through the peripheral bus controller
J
EMIF
The DMA controller requests reads and writes to internal data memory.
The CPU cannot access internal program memory through the data
memory controller.
The CPU sends requests to the data memory controller through the two address
buses (DA1 and DA2). Store data is transmitted through the CPU data store
buses (ST1 and ST2). Load data is received through the CPU data load buses
(LD1 and LD2). The CPU data requests are mapped, based on address, to
either the internal data memory, internal peripheral space (through the peripher-
al bus controller), or the external memory interface. The data memory controller
also connects the DMA controller to the internal data memory and performs ar-
bitration between the CPU and DMA controller.