Synchronous-Burst Memory Timing - Texas Instruments TMS320C6201 Manual

timing requirements for synchronous-burst SRAM cycles (full-rate SSCLK) (see Figure 17)
NO. NO
7 t
su(EDV-SSCLKH)
8 t
h(SSCLKH-EDV)
switching characteristics over recommended operating conditions for synchronous-burst SRAM
†
cycles (full-rate SSCLK) (see Figure 17 and Figure 18)
NO. NO
1 t
osu(CEV-SSCLKH)
2 t
oh(SSCLKH-CEV)
3 t
osu(BEV-SSCLKH)
4 t
oh(SSCLKH-BEIV)
5 t
osu(EAV-SSCLKH)
6 t
oh(SSCLKH-EAIV)
9 t
osu(ADSV-SSCLKH)
10 t
oh(SSCLKH-ADSV)
11 t
osu(OEV-SSCLKH)
12 t
oh(SSCLKH-OEV)
13 t
osu(EDV-SSCLKH)
14 t
oh(SSCLKH-EDIV)
15 t
osu(WEV-SSCLKH)
16 t
oh(SSCLKH-WEV)
†
When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For CLKMODE x1, 0.5P is defined as PH (pulse duration of CLKIN high) for all output setup times; 0.5P is defined as PL (pulse duration of CLKIN
low) for all output hold times.

SYNCHRONOUS-BURST MEMORY TIMING

Setup time, read EDx valid before SSCLK high
Hold time, read EDx valid after SSCLK high
PARAMETER PARAMETER
Output setup time, CEx valid before SSCLK high
Output hold time, CEx valid after SSCLK high
Output setup time, BEx valid before SSCLK high
Output hold time, BEx invalid after SSCLK high
Output setup time, EAx valid before SSCLK high
Output hold time, EAx invalid after SSCLK high
Output setup time, SSADS valid before SSCLK high
Output hold time, SSADS valid after SSCLK high
Output setup time, SSOE valid before SSCLK high
Output hold time, SSOE valid after SSCLK high
Output setup time, EDx valid before SSCLK high
Output hold time, EDx invalid after SSCLK high
Output setup time, SSWE valid before SSCLK high
Output hold time, SSWE valid after SSCLK high
POST OFFICE BOX 1443
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
•
HOUSTON, TEXAS 77251--1443
TMS320C6201
- -200
UNIT UNIT
MIN MAX
1.5 ns
1.5 ns
- -200
UNIT UNIT
MIN MAX
0.5P -- 1.3 ns
0.5P -- 2.3 ns
0.5P -- 1.3 ns
0.5P -- 2.3 ns
0.5P -- 1.3 ns
0.5P -- 2.3 ns
0.5P -- 1.3 ns
0.5P -- 2.3 ns
0.5P -- 1.3 ns
0.5P -- 2.3 ns
0.5P -- 1.3 ns
0.5P -- 2.3 ns
0.5P -- 1.3 ns
0.5P -- 2.3 ns
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