User Manuals: HOLTEK HT32F52230 32-bit microcontroller

Manuals and User Guides for HOLTEK HT32F52230 32-bit microcontroller. We have 1 HOLTEK HT32F52230 32-bit microcontroller manual available for free PDF download: User Manual

HOLTEK HT32F52230 User Manual (366 pages)

32-Bit Microcontroller with Arm Cortex-M0+ Core

Brand: HOLTEK | Category: Microcontrollers | Size: 3 MB

Table of Contents
2
1 Introduction

17
- Overview
  17
- Features
  18
- Device Information
  21
- Table 1. Features and Peripheral List
  21
- Block Diagram
  22
- Figure 1. Block Diagram
  22
2 Document Conventions

23
- Table 2. Document Conventions
  23
3 System Architecture

24
- Arm ® Cortex ® -M0+ Processor
  24
- Bus Architecture
  25
- Figure 2. Cortex ® -M0+ Block Diagram
  25
- Memory Organization
  26
  - Figure 3. Bus Architecture
    26
  - Figure 4. Memory Map
    27
  - Memory Map
    27
  - Table 3. Register Map
    28
  - AHB Peripherals
    29
  - APB Peripherals
    29
  - Embedded Flash Memory
    29
  - Embedded SRAM Memory
    29
4 Flash Memory Controller (FMC)

30
5 Power Control Unit (PWRCU)

57
6 Clock Control Unit (CKCU)

69
7 Reset Control Unit (RSTCU)

98
- Introduction
  98
- Figure 16. RSTCU Block Diagram
  98
- Functional Descriptions
  99
  - Power on Reset
    99
  - System Reset
    99
  - AHB and APB Unit Reset
    99
  - Figure 17. Power on Reset Sequence
    99
- Register Map
  100
- Register Descriptions
  100
8 General Purpose I/O (GPIO)

104
9 Alternate Function Input/Output Control Unit (AFIO)

130
- Introduction
  130
- Figure 20. AFIO Block Diagram
  130
- Features
  131
- Functional Descriptions
  131
  - External Interrupt Pin Selection
    131
  - Figure 21. EXTI Channel Input Selection
    131
  - Alternate Function
    132
  - Lock Mechanism
    132
- Register Map
  132
- Table 22. AFIO Selection for Peripheral Map Example
  132
- Table 23. AFIO Register Map
  132
- Register Descriptions
  133
10 Nested Vectored Interrupt Controller (NVIC)

137
- Introduction
  137
- Table 24. Exception Types
  137
- Features
  138
- Function Descriptions
  139
  - Systick Calibration
    139
- Register Map
  139
- Table 25. NVIC Register Map
  139
11 External Interrupt/Event Controller (EXTI)

140
12 Analog to Digital Converter (ADC)

152
- Introduction
  152
- Figure 25. ADC Block Diagram
  152
- Features
  153
- Function Descriptions
  154
  - ADC Clock Setup
    154
  - Channel Selection
    154
  - Conversion Mode
    154
  - Figure 26. One Shot Conversion Mode
    155
  - Figure 27. Continuous Conversion Mode
    155
  - Start Conversion on External Event
    157
  - Figure 28. Discontinuous Conversion Mode
    157
  - Sampling Time Setting
    158
  - Data Format
    158
  - Analog Watchdog
    158
  - Table 27. Data Format in ADCDR [15:0]
    158
  - Interrupts
    159
- Register Map
  160
- Table 28. A/D Converter Register Map
  160
- Register Descriptions
  161
13 General-Purpose Timer (GPTM)

175
14 Basic Function Timer (BFTM)

236
- Introduction
  236
- Features
  236
- Figure 59. BFTM Block Diagram
  236
- Functional Description
  237
  - Repetitive Mode
    237
  - Figure 60. BFTM - Repetitive Mode
    237
  - One Shot Mode
    238
  - Trigger ADC Start
    238
  - Figure 61. BFTM - One Shot Mode
    238
  - Figure 62. BFTM - One Shot Mode Counter Updating
    238
- Register Map
  239
- Register Descriptions
  239
  - BFTM Control Register - BFTMCR
    239
  - Table 33. BFTM Register Map
    239
  - BFTM Status Register - BFTMSR
    240
  - BFTM Counter Register - BFTMCNTR
    241
  - BFTM Compare Value Register - BFTMCMPR
    241
15 Single-Channel Timer (SCTM)

242
- Introduction
  242
- Figure 63. SCTM Block Diagram
  242
- Features
  243
- Functional Descriptions
  243
  - Counter Mode
    243
  - Figure 64. Up-Counting Example
    243
  - Clock Controller
    244
  - Figure 65. SCTM Clock Selection Source
    244
  - Trigger Controller
    245
  - Figure 66. Trigger Control Block
    245
  - Slave Controller
    246
  - Figure 67. Slave Controller Diagram
    246
  - Figure 68. SCTM in Restart Mode
    246
  - Figure 69. SCTM in Pause Mode
    247
  - Figure 70. SCTM in Trigger Mode
    247
  - Channel Controller
    248
  - Figure 71. Capture/Compare Block Diagram
    248
  - Figure 72. Input Capture Mode
    248
  - Input Stage
    249
  - Figure 73. Channel Input Stages
    249
  - Figure 74. TI Digital Filter Diagram with N = 2
    249
  - Output Stage
    250
  - Table 34. Compare Match Output Setup
    250
  - Figure 75. Output Stage Block Diagram
    250
  - Figure 76. Toggle Mode Channel Output Reference Signal - CHPRE = 0
    251
  - Figure 77. Toggle Mode Channel Output Reference Signal - CHPRE = 1
    251
  - Update Management
    252
  - Figure 78. PWM Mode Channel Output Reference Signal
    252
- Register Map
  253
- Table 35. SCTM Register Map
  253
- Figure 79. Update Event Setting Diagram
  253
- Register Descriptions
  254
16 Watchdog Timer (WDT)

269
- Introduction
  269
- Features
  269
- Figure 80. Watchdog Timer Block Diagram
  269
- Functional Description
  270
- Figure 81. Watchdog Timer Behavior
  271
- Register Map
  272
- Register Descriptions
  272
17 Inter-Integrated Circuit (I C)

278
- Introduction
  278
- Figure 82. I 2 C Module Block Diagram
  278
- Features
  279
- Functional Descriptions
  279
  - Two Wire Serial Interface
    279
  - START and STOP Conditions
    279
  - Data Validity
    280
  - Figure 83. START and STOP Condition
    280
  - Figure 84. Data Validity
    280
  - Addressing Format
    281
  - Figure 85. 7-Bit Addressing Mode
    281
  - Figure 86. 10-Bit Addressing Write Transmit Mode
    282
  - Figure 87. 10-Bits Addressing Read Receive Mode
    282
  - Data Transfer and Acknowledge
    283
  - Figure 88. I 2 C Bus Acknowledge
    283
  - Clock Synchronization
    284
  - Arbitration
    284
  - Figure 89. Clock Synchronization During Arbitration
    284
  - Figure 90. Two Master Arbitration Procedure
    284
  - General Call Addressing
    285
  - Bus Error
    285
  - Address Mask Enable
    285
  - Address Snoop
    285
  - Operation Mode
    285
  - Figure 91. Master Transmitter Timing Diagram
    286
  - Figure 92. Master Receiver Timing Diagram
    288
  - Figure 93. Slave Transmitter Timing Diagram
    289
  - Figure 94. Slave Receiver Timing Diagram
    290
  - Conditions of Holding SCL Line
    291
  - Table 37. Conditions of Holding SCL Line
    291
  - I 2 C Timeout Function
    292
- Register Map
  292
- Table 38. I 2 C Register Map
  292
- Register Descriptions
  293
18 Serial Peripheral Interface (SPI)

307
19 Universal Synchronous Asynchronous Receiver Transmitter (USART)

326
20 Universal Asynchronous Receiver Transmitter (UART)

354

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User Manuals: HOLTEK HT32F52230 32-bit microcontroller

HOLTEK HT32F52230 User Manual (366 pages)

Table of Contents

1 Introduction

2 Document Conventions

3 System Architecture

4 Flash Memory Controller (FMC)

5 Power Control Unit (PWRCU)

6 Clock Control Unit (CKCU)

7 Reset Control Unit (RSTCU)

8 General Purpose I/O (GPIO)

9 Alternate Function Input/Output Control Unit (AFIO)

10 Nested Vectored Interrupt Controller (NVIC)

11 External Interrupt/Event Controller (EXTI)

12 Analog to Digital Converter (ADC)

13 General-Purpose Timer (GPTM)

14 Basic Function Timer (BFTM)

15 Single-Channel Timer (SCTM)

16 Watchdog Timer (WDT)

17 Inter-Integrated Circuit (I C)

18 Serial Peripheral Interface (SPI)

19 Universal Synchronous Asynchronous Receiver Transmitter (USART)

20 Universal Asynchronous Receiver Transmitter (UART)

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