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HT32F52352
User Manuals: HOLTEK HT32F52352 32-bit USB MCU
Manuals and User Guides for HOLTEK HT32F52352 32-bit USB MCU. We have
3
HOLTEK HT32F52352 32-bit USB MCU manuals available for free PDF download: User Manual, Manualline, Firmware Manual
HOLTEK HT32F52352 User Manual (656 pages)
32-Bit Microcontroller with Arm Cortex-M0+ Core
Brand:
HOLTEK
| Category:
Microcontrollers
| Size: 6 MB
Table of Contents
Table of Contents
2
1 Introduction
26
Overview
26
Features
27
Device Information
32
Table 1. Series Features and Peripheral List
32
Block Diagram
33
Figure 1. Block Diagram
33
2 Document Conventions
34
Table 2. Document Conventions
34
3 System Architecture
35
Arm ® Cortex ® -M0+ Processor
35
Bus Architecture
36
Figure 2. Cortex ® -M0+ Block Diagram
36
Memory Organization
37
Figure 3. Bus Architecture
37
Figure 4. Memory Map
38
Memory Map
38
Table 3. Register Map
39
AHB Peripherals
41
APB Peripherals
41
Embedded Flash Memory
41
Embedded SRAM Memory
41
4 Flash Memory Controller (FMC)
42
Introduction
42
Features
42
Figure 5. Flash Memory Controller Block Diagram
42
Functional Descriptions
43
Flash Memory Map
43
Figure 6. Flash Memory Map
43
Flash Memory Architecture
44
Wait State Setting
44
Table 4. Flash Memory and Option Byte
44
Table 5. Relationship between Wait State Cycle and HCLK
44
Booting Configuration
45
Table 6. Booting Modes
45
Figure 7. Vector Remapping
45
Page Erase
46
Figure 8. Page Erase Operation Flowchart
46
Mass Erase
47
Figure 9. Mass Erase Operation Flowchart
47
Word Programming
48
Figure 10. Word Programming Operation Flowchart
48
Option Byte Description
49
Page Erase/Program Protection
49
Table 7. Option Byte Memory Map
49
Table 8. Access Permission of Protected Main Flash Page
50
Security Protection
51
Table 9. Access Permission When Security Protection Is Enabled
51
Register Map
52
Table 10. FMC Register Map
52
Register Descriptions
53
Flash Target Address Register - TADR
53
Flash Write Data Register - WRDR
54
Flash Operation Command Register - OCMR
55
Flash Operation Control Register - OPCR
56
Flash Operation Interrupt Enable Register - OIER
57
Flash Operation Interrupt and Status Register - OISR
58
Flash Page Erase/Program Protection Status Register - PPSR
60
Flash Security Protection Status Register - CPSR
61
Flash Vector Mapping Control Register - VMCR
62
Flash Manufacturer and Device ID Register - MDID
63
Flash Page Number Status Register - PNSR
64
Flash Page Size Status Register - PSSR
65
Flash Cache & Pre-Fetch Control Register - CFCR
66
Custom ID Register N - Cidrn, N = 0 ~ 3
67
5 Power Control Unit (PWRCU)
68
Introduction
68
Figure 11. PWRCU Block Diagram
68
Features
69
Functional Descriptions
69
Backup Domain
69
VDD Power Domain
70
Figure 12. Power on Reset / Power down Reset Waveform
71
1.5 V Power Domain
72
Operation Modes
72
Table 11. Operation Mode Definitions
72
Table 12. Enter/Exit Power Saving Modes
73
Register Map
74
Table 13. Power Status after System Reset
74
Table 14. PWRCU Register Map
74
Register Descriptions
75
Backup Domain Status Register - BAKSR
75
Backup Domain Control Register - BAKCR
76
Backup Domain Test Register - BAKTEST
78
Low Voltage / Brown out Detect Control and Status Register - LVDCSR
79
Backup Register N - Bakregn, N = 0 ~ 9
81
6 Clock Control Unit (CKCU)
82
Introduction
82
Figure 13. CKCU Block Diagram
83
Features
84
Function Descriptions
84
High Speed External Crystal Oscillator - HSE
84
Figure 14. External Crystal, Ceramic, and Resonators for HSE
84
High Speed Internal RC Oscillator - HSI
85
Auto Trimming of High Speed Internal RC Oscillator - HSI
85
Figure 15. HSI Auto Trimming Block Diagram
86
Phase Locked Loop - PLL
87
Figure 16. PLL Block Diagram
87
Table 15. Output Divider2 Value Mapping
88
Table 16. Feedback Divider2 Value Mapping
88
Low Speed External Crystal Oscillator - LSE
89
Low Speed Internal RC Oscillator - LSI
89
Clock Ready Flag
89
Figure 17. External Crystal, Ceramic, and Resonators for LSE
89
System Clock (CK_SYS) Selection
90
HSE Clock Monitor
91
Clock Output Capability
91
Table 17. CKOUT Clock Source
91
Register Map
92
Table 18. CKCU Register Map
92
Register Descriptions
93
Global Clock Configuration Register - GCFGR
93
Global Clock Control Register - GCCR
95
Global Clock Status Register - GCSR
97
Global Clock Interrupt Register - GCIR
98
PLL Configuration Register - PLLCFGR
99
PLL Control Register - PLLCR
99
AHB Configuration Register - AHBCFGR
100
AHB Clock Control Register - AHBCCR
101
APB Configuration Register - APBCFGR
103
APB Clock Control Register 0 - APBCCR0
104
APB Clock Control Register 1 - APBCCR1
106
Clock Source Status Register - CKST
108
APB Peripheral Clock Selection Register 0 - APBPCSR0
109
APB Peripheral Clock Selection Register 1 - APBPCSR1
111
HSI Control Register - HSICR
113
HSI Auto Trimming Counter Register - HSIATCR
114
Low Power Control Register - LPCR
115
MCU Debug Control Register - MCUDBGCR
116
7 Reset Control Unit (RSTCU)
119
Introduction
119
Figure 18. RSTCU Block Diagram
119
Functional Descriptions
120
Power on Reset
120
System Reset
120
AHB and APB Unit Reset
120
Figure 19. Power on Reset Sequence
120
Register Map
121
Register Descriptions
121
Global Reset Status Register - GRSR
121
Table 19. RSTCU Register Map
121
AHB Peripheral Reset Register - AHBPRSTR
122
APB Peripheral Reset Register 0 - APBPRSTR0
123
APB Peripheral Reset Register 1 - APBPRSTR1
125
8 General Purpose I/O (GPIO)
127
Introduction
127
Figure 20. GPIO Block Diagram
127
Features
128
Functional Descriptions
128
Default GPIO Pin Configuration
128
General Purpose I/O - GPIO
128
Table 20. AFIO, GPIO and IO Pad Control Signal True Table
129
Figure 21. AFIO/GPIO Control Signal
129
GPIO Locking Mechanism
130
Register Map
130
Table 21. GPIO Register Map
130
Register Descriptions
131
Port a Data Direction Control Register - PADIRCR
131
Port a Input Function Enable Control Register - PAINER
132
Port a Pull-Up Selection Register - PAPUR
133
Port a Pull-Down Selection Register - PAPDR
134
Port a Open Drain Selection Register - PAODR
135
Port a Output Current Drive Selection Register - PADRVR
136
Port a Lock Register - PALOCKR
137
Port a Data Input Register - PADINR
138
Port a Output Data Register - PADOUTR
139
Port a Output Set/Reset Control Register - PASRR
140
Port a Output Reset Register - PARR
141
Port B Data Direction Control Register - PBDIRCR
142
Port B Input Function Enable Control Register - PBINER
143
Port B Pull-Up Selection Register - PBPUR
144
Port B Pull-Down Selection Register - PBPDR
145
Port B Open Drain Selection Register - PBODR
146
Port B Output Current Drive Selection Register - PBDRVR
147
Port B Lock Register - PBLOCKR
148
Port B Data Input Register - PBDINR
149
Port B Output Data Register - PBDOUTR
150
Port B Output Set/Reset Control Register - PBSRR
151
Port B Output Reset Register - PBRR
152
Port C Data Direction Control Register - PCDIRCR
153
Port C Input Function Enable Control Register - PCINER
154
Port C Pull-Up Selection Register - PCPUR
155
Port C Pull-Down Selection Register - PCPDR
156
Port C Open Drain Selection Register - PCODR
157
Port C Output Current Drive Selection Register - PCDRVR
158
Port C Lock Register - PCLOCKR
159
Port C Data Input Register - PCDINR
160
Port C Output Data Register - PCDOUTR
161
Port C Output Set/Reset Control Register - PCSRR
162
Port C Output Reset Register - PCRR
163
Port D Data Direction Control Register - PDDIRCR
164
Port D Input Function Enable Control Register - PDINER
165
Port D Pull-Up Selection Register - PDPUR
166
Port D Pull-Down Selection Register - PDPDR
167
Port D Open Drain Selection Register - PDODR
168
Port D Output Current Drive Selection Register - PDDRVR
169
Port D Lock Register - PDLOCKR
170
Port D Data Input Register - PDDINR
171
Port D Output Data Register - PDDOUTR
172
Port D Output Set/Reset Control Register - PDSRR
173
Port D Output Reset Register - PDRR
174
9 Alternate Function Input/Output Control Unit (AFIO)
175
Introduction
175
Figure 22. AFIO Block Diagram
175
Features
176
Functional Descriptions
176
External Interrupt Pin Selection
176
Figure 23. EXTI Channel Input Selection
176
Alternate Function
177
Lock Mechanism
177
Register Map
177
Table 22. AFIO Selection for Peripheral Map Example
177
Table 23. AFIO Register Map
177
Register Descriptions
178
EXTI Source Selection Register 0 - ESSR0
178
EXTI Source Selection Register 1 - ESSR1
179
GPIO X Configuration Low Register - Gpxcfglr, X = A, B, C, D
180
GPIO X Configuration High Register - Gpxcfghr, X = A, B, C, D
181
10 Nested Vectored Interrupt Controller (NVIC)
182
Introduction
182
Table 24. Exception Types
182
Features
183
Function Descriptions
184
Systick Calibration
184
Register Map
184
Table 25. NVIC Register Map
184
11 External Interrupt/Event Controller (EXTI)
185
Introduction
185
Features
185
Figure 24. EXTI Block Diagram
185
Function Descriptions
186
Wakeup Event Management
186
Figure 25. EXTI Wake-Up Event Management
186
External Interrupt/Event Line Mapping
187
Interrupt and Debounce
187
Figure 26. EXTI Interrupt Debounce Function
187
Register Map
188
Table 26. EXTI Register Map
188
Register Descriptions
189
EXTI Interrupt Configuration Register N - Exticfgrn, N = 0 ~ 15
189
EXTI Interrupt Control Register - EXTICR
190
EXTI Interrupt Edge Flag Register - EXTIEDGEFLGR
191
EXTI Interrupt Edge Status Register - EXTIEDGESR
192
EXTI Interrupt Software Set Command Register - EXTISSCR
193
EXTI Interrupt Wakeup Control Register - EXTIWAKUPCR
194
EXTI Interrupt Wakeup Polarity Register - EXTIWAKUPPOLR
195
EXTI Interrupt Wakeup Flag Register - EXTIWAKUPFLG
196
12 Analog to Digital Converter (ADC)
197
Introduction
197
Figure 27. ADC Block Diagram
197
Features
198
Function Descriptions
199
ADC Clock Setup
199
Channel Selection
199
Conversion Mode
199
Figure 28. One Shot Conversion Mode
200
Figure 29. Continuous Conversion Mode
200
Start Conversion on External Event
202
Figure 30. Discontinuous Conversion Mode
202
Sampling Time Setting
203
Data Format
203
Analog Watchdog
203
Table 27. Data Format in ADCDR [15:0]
203
Interrupts
204
PDMA Request
204
Register Map
205
Table 28. A/D Converter Register Map
205
Register Descriptions
206
ADC Conversion Control Register - ADCCR
206
ADC Conversion List Register 0 - ADCLST0
208
ADC Conversion List Register 1 - ADCLST1
209
ADC Input Sampling Time Register - ADCSTR
210
ADC Conversion Data Register y - Adcdry, y = 0 ~ 7
211
ADC Trigger Control Register - ADCTCR
212
ADC Trigger Source Register - ADCTSR
213
ADC Watchdog Control Register - ADCWCR
214
ADC Watchdog Threshold Register - ADCTR
215
ADC Interrupt Enable Register - ADCIER
216
ADC Interrupt Raw Status Register - ADCIRAW
217
ADC Interrupt Status Register - ADCISR
218
ADC Interrupt Clear Register - ADCICLR
219
ADC DMA Request Register - ADCDMAR
220
13 Comparator (CMP)
221
Introduction
221
Features
221
Figure 31. Comparator Block Diagram
221
Function Descriptions
222
Comparator Inputs and Output
222
Comparator Voltage Reference
222
Figure 32. 6-Bit Scaler for Comparator Voltage Reference Block Diagram
222
Interrupts and Wakeup
223
Figure 33. Interrupt Signals of Comparators
223
Figure 34. Wakeup Signals of Comparators
223
Power Mode and Hysteresis
224
Comparator Write-Protected Mechanism
224
Register Map
224
Table 29. CMP Register Map
224
Register Descriptions
225
Comparator Control Register N - Cmpcrn, N = 0 or 1
225
Comparator Voltage Reference Value Register N - Cvrvalrn, N = 0 or 1
227
Comparator Interrupt Enable Register N - Cmpiern, N = 0 or 1
228
Comparator Transition Flag Register N - Cmptfrn, N = 0 or 1
229
14 General-Purpose Timer (GPTM)
230
Introduction
230
Figure 35. GPTM Block Diagram
230
Features
231
Functional Descriptions
232
Counter Mode
232
Figure 36. Up-Counting Example
232
Figure 37. Down-Counting Example
233
Figure 38. Center-Aligned Counting Example
234
Clock Controller
235
Figure 39. GPTM Clock Selection Source
235
Trigger Controller
236
Figure 40. Trigger Controller Block
236
Slave Controller
237
Figure 41. Slave Controller Diagram
237
Figure 42. GPTM in Restart Mode
237
Figure 43. GPTM in Pause Mode
238
Figure 44. GPTM in Trigger Mode
239
Master Controller
240
Figure 45. Master Gptmn and Slave Gptmm/Mctmm Connection
240
Figure 46. MTO Selection
240
Channel Controller
241
Figure 47. Capture/Compare Block Diagram
241
Figure 48. Input Capture Mode
242
Figure 49. PWM Pulse Width Measurement Example
243
Input Stage
244
Figure 50. Channel 0 and Channel 1 Input Stages
244
Figure 51. Channel 2 and Channel 3 Input Stages
245
Figure 52. TI0 Digital Filter Diagram with N = 2
245
Quadrature Decoder
246
Figure 53. Input Stage and Quadrature Decoder Block Diagram
246
Table 30. Counting Direction and Encoding Signals
247
Figure 54. both TI0 and TI1 Quadrature Decoder Counting
247
Output Stage
248
Table 31. Compare Match Output Setup
248
Figure 55. Output Stage Block Diagram
248
Figure 56. Toggle Mode Channel Output Reference Signal (Chxpre = 0)
249
Figure 57. Toggle Mode Channel Output Reference Signal (Chxpre = 1)
249
Figure 58. PWM Mode Channel Output Reference Signal and Counter in Up-Counting Mode
250
Figure 59. PWM Mode Channel Output Reference Signal and Counter in Down-Counting Mode
250
Figure 60. PWM Mode Channel Output Reference Signal and Counter in Centre-Align Mode
251
Update Management
252
Figure 61. Update Event Setting Diagram
252
Single Pulse Mode
253
Figure 62. Single Pulse Mode
253
Figure 63. Immediate Active Mode Minimum Delay
254
Asymmetric PWM Mode
255
Figure 64. Asymmetric PWM Mode Versus Center Align Counting Mode
255
Timer Interconnection
256
Figure 65. Pausing GPTM1 Using the GPTM0 CH0OREF Signal
256
Figure 66. Triggering GPTM1 with GPTM0 Update Event
257
Figure 67. Trigger GPTM0 and GPTM1 with the GPTM0 CH0 Input
258
Trigger ADC Start
259
PDMA Request
259
Figure 68. GPTM PDMA Mapping Diagram
259
Register Map
260
Table 32. GPTM Register Map
260
Register Descriptions
261
Timer Counter Configuration Register - CNTCFR
261
Timer Mode Configuration Register - MDCFR
263
Timer Trigger Configuration Register - TRCFR
266
Table 33. GPTM Internal Trigger Connection
266
Timer Counter Register - CTR
267
Channel 0 Input Configuration Register - CH0ICFR
268
Channel 1 Input Configuration Register - CH1ICFR
270
Channel 2 Input Configuration Register - CH2ICFR
272
Channel 3 Input Configuration Register - CH3ICFR
274
Channel 0 Output Configuration Register - CH0OCFR
276
Channel 1 Output Configuration Register - CH1OCFR
278
Channel 2 Output Configuration Register - CH2OCFR
280
Channel 3 Output Configuration Register - CH3OCFR
282
Channel Control Register - CHCTR
284
Channel Polarity Configuration Register - CHPOLR
285
Timer Pdma/Interrupt Control Register - DICTR
286
Timer Event Generator Register - EVGR
288
Timer Interrupt Status Register - INTSR
290
Timer Counter Register - CNTR
293
Timer Prescaler Register - PSCR
294
Timer Counter Reload Register - CRR
295
Channel 0 Capture/Compare Register - CH0CCR
296
Channel 1 Capture/Compare Register - CH1CCR
297
Channel 2 Capture/Compare Register - CH2CCR
298
Channel 3 Capture/Compare Register - CH3CCR
299
Channel 0 Asymmetric Compare Register - CH0ACR
300
Channel 1 Asymmetric Compare Register - CH1ACR
301
Channel 2 Asymmetric Compare Register - CH2ACR
302
Channel 3 Asymmetric Compare Register - CH3ACR
303
15 Basic Function Timer (BFTM)
304
Introduction
304
Features
304
Figure 69. BFTM Block Diagram
304
Functional Description
305
Repetitive Mode
305
Figure 70. BFTM - Repetitive Mode
305
One Shot Mode
306
Figure 71. BFTM - One Shot Mode
306
Figure 72. BFTM - One Shot Mode Counter Updating
306
Register Map
307
Register Descriptions
307
BFTM Control Register - BFTMCR
307
Table 34. BFTM Register Map
307
BFTM Status Register - BFTMSR
308
BFTM Counter Register - BFTMCNTR
309
BFTM Compare Value Register - BFTMCMPR
310
16 Motor Control Timer (MCTM)
311
Introduction
311
Figure 73. MCTM Block Diagram
311
Features
312
Functional Descriptions
313
Counter Mode
313
Figure 74. Up-Counting Example
313
Figure 75. Down-Counting Example
314
Figure 76. Center-Aligned Counting Example
315
Figure 77. Update Event 1 Dependent Repetition Mechanism Example
316
Clock Controller
317
Figure 78. MCTM Clock Selection Source
317
Trigger Controller
318
Figure 79. Trigger Controller Block
318
Slave Controller
319
Figure 80. Slave Controller Diagram
319
Figure 81. MCTM in Restart Mode
319
Figure 82. MCTM in Pause Mode
320
Figure 83. MCTM in Trigger Mode
320
Master Controller
321
Figure 84. Master Mctmn and Slave Gptmm Connection
321
Figure 85. MTO Selection
321
Channel Controller
322
Figure 86. Capture/Compare Block Diagram
322
Figure 87. Input Capture Mode
323
Figure 88. PWM Pulse Width Measurement Example
324
Input Stage
325
Figure 89. Channel 0 and Channel 1 Input Stages
325
Figure 90. Channel 2 and Channel 3 Input Stages
325
Figure 91. TI0 Digital Filter Diagram with N = 2
326
Output Stage
327
Figure 92. Output Stage Block Diagram
327
Table 35. Compare Match Output Setup
328
Figure 93. Toggle Mode Channel Output Reference Signal - Chxpre = 0
328
Figure 94. Toggle Mode Channel Output Reference Signal - Chxpre = 1
329
Figure 95. PWM Mode Channel Output Reference Signal and Counter in Up-Counting Mode
329
Figure 96. PWM Mode Channel Output Reference Signal and Counter in Down-Counting Mode
330
Figure 97. PWM Mode 1 Channel Output Reference Signal and Counter in Centre-Aligned Counting
330
Figure 98. Dead-Time Insertion Performed for Complementary Outputs
331
Figure 99. MCTM Break Signal Bolck Diagram
332
Figure 100. MT_BRK Pin Digital Filter Diagram with N = 2
332
Figure 101. Channel 3 Output with a Break Event Occurrence
333
Figure 102. Channel 0 ~ 2 Complementary Outputs with a Break Event Occurrence
334
Figure 103. Channel 0 ~ 2 Only One Output Enabled When Fault Event Occurs
334
Figure 104. Hardware Protection When both Chxo and Chxno Are in Active Condition
335
Table 36. Output Control Bits for Complementary Output with a Break Event Occurrence
336
Update Management
337
Figure 105. Update Event 1 Setup Diagram
337
Figure 106. Chxe, Chxne and Chxom Updated by Update Event 2
338
Figure 107. Update Event 2 Setup Diagram
338
Single Pulse Mode
339
Figure 108. Single Pulse Mode
339
Figure 109. Immediate Active Mode Minimum Delay
340
Asymmetric PWM Mode
341
Figure 110. Asymmetric PWM Mode Versus Center-Aligned Counting Mode
341
Timer Interconnection
342
Figure 111. Pausing GPTM Using the MCTM CH0OREF Signal
342
Figure 112. Triggering GPTM with MCTM Update Event 1
343
Figure 113. Trigger MCTM and GPTM with the MCTM CH0 Input
344
Figure 114. CH1XOR Input as Hall Sensor Interface
345
Trigger ADC Start
346
Lock Level Table
346
Table 37. Lock Level Table
346
PDMA Request
347
Figure 115. MCTM PDMA Mapping Diagram
347
Register Map
348
Table 38. MCTM Register Map
348
Register Descriptions
349
Timer Counter Configuration Register - CNTCFR
349
Timer Mode Configuration Register - MDCFR
351
Timer Trigger Configuration Register - TRCFR
354
Table 39. MCTM Internal Trigger Connection
354
Timer Counter Register - CTR
355
Channel 0 Input Configuration Register - CH0ICFR
356
Channel 1 Input Configuration Register - CH1ICFR
358
Channel 2 Input Configuration Register - CH2ICFR
360
Channel 3 Input Configuration Register - CH3ICFR
362
Channel 0 Output Configuration Register - CH0OCFR
364
Channel 1 Output Configuration Register - CH1OCFR
366
Channel 2 Output Configuration Register - CH2OCFR
368
Channel 3 Output Configuration Register - CH3OCFR
370
Channel Control Register - CHCTR
372
Channel Polarity Configuration Register - CHPOLR
374
Channel Break Configuration Register - CHBRKCFR
376
Channel Break Control Register - CHBRKCTR
377
Timer Pdma/Interrupt Control Register - DICTR
379
Timer Event Generator Register - EVGR
381
Timer Interrupt Status Register - INTSR
383
Timer Counter Register - CNTR
386
Timer Prescaler Register - PSCR
387
Timer Counter Reload Register - CRR
388
Timer Repetition Register - REPR
389
Channel 0 Capture/Compare Register - CH0CCR
390
Channel 1 Capture/Compare Register - CH1CCR
391
Channel 2 Capture/Compare Register - CH2CCR
392
Channel 3 Capture/Compare Register - CH3CCR
393
Channel 0 Asymmetric Compare Register - CH0ACR
394
Channel 1 Asymmetric Compare Register - CH1ACR
395
Channel 2 Asymmetric Compare Register - CH2ACR
396
Channel 3 Asymmetric Compare Register - CH3ACR
397
17 Single-Channel Timer (SCTM)
398
Introduction
398
Figure 116. SCTM Block Diagram
398
Features
399
Functional Descriptions
399
Counter Mode
399
Figure 117. Up-Counting Example
399
Clock Controller
400
Figure 118. SCTM Clock Selection Source
400
Trigger Controller
401
Figure 119. Trigger Controller Block
401
Slave Controller
402
Figure 120. Slave Controller Diagram
402
Figure 121. SCTM in Restart Mode
402
Figure 122. SCTM in Pause Mode
403
Figure 123. SCTM in Trigger Mode
403
Channel Controller
404
Figure 124. Capture/Compare Block Diagram
404
Figure 125. Input Capture Mode
405
Input Stage
406
Figure 126. Channel Input Stages
406
Figure 127. TI Digital Filter Diagram with N = 2
406
Output Stage
407
Table 40. Compare Match Output Setup
407
Figure 128. Output Stage Block Diagram
407
Figure 129. Toggle Mode Channel Output Reference Signal (CHPRE = 0)
408
Figure 130. Toggle Mode Channel Output Reference Signal (CHPRE = 1)
408
Update Management
409
Figure 131. PWM Mode Channel Output Reference Signal
409
Register Map
410
Table 41. SCTM Register Map
410
Figure 132. Update Event Setting Diagram
410
Register Descriptions
411
Timer Counter Configuration Register - CNTCFR
411
Timer Mode Configuration Register - MDCFR
412
Timer Trigger Configuration Register - TRCFR
413
Timer Counter Register - CTR
414
Channel Input Configuration Register - CHICFR
415
Channel Output Configuration Register - CHOCFR
417
Channel Control Register - CHCTR
418
Channel Polarity Configuration Register - CHPOLR
419
Timer Interrupt Control Register - DICTR
420
Timer Event Generator Register - EVGR
421
Timer Interrupt Status Register - INTSR
422
Timer Counter Register - CNTR
423
Timer Prescaler Register - PSCR
424
Timer Counter Reload Register - CRR
425
Channel Capture/Compare Register - CHCCR
426
18 Real Time Clock (RTC)
427
Introduction
427
Features
427
Figure 133. RTC Block Diagram
427
Functional Descriptions
428
RTC Related Register Reset
428
Reading RTC Register
428
Low Speed Clock Configuration
428
Table 42. LSE Startup Mode Operating Current and Startup Time
428
RTC Counter Operation
429
Interrupt and Wakeup Control
429
RTCOUT Output Pin Configuration
430
Table 43. RTCOUT Output Mode and Active Level Setting
430
Register Map
431
Register Descriptions
431
RTC Counter Register - RTCCNT
431
Table 44. RTC Register Map
431
RTC Compare Register - RTCCMP
432
RTC Control Register - RTCCR
433
RTC Status Register - RTCSR
435
RTC Interrupt and Wakeup Enable Register - RTCIWEN
436
19 Watchdog Timer (WDT)
437
Introduction
437
Features
437
Figure 134. Watchdog Timer Block Diagram
437
Functional Description
438
Figure 135. Watchdog Timer Behavior
439
Register Map
440
Register Descriptions
440
Watchdog Timer Control Register - WDTCR
440
Table 45. Watchdog Timer Register Map
440
Watchdog Timer Mode Register 0 - WDTMR0
441
Watchdog Timer Mode Register 1 - WDTMR1
442
Watchdog Timer Status Register - WDTSR
443
Watchdog Timer Protection Register - WDTPR
444
Watchdog Timer Clock Selection Register - WDTCSR
445
20 Inter-Integrated Circuit (I C)
446
Introduction
446
Figure 136. I C Module Block Diagram
446
Features
447
Functional Descriptions
447
Two Wire Serial Interface
447
START and STOP Conditions
447
Data Validity
448
Figure 137. START and STOP Condition
448
Figure 138. Data Validity
448
Addressing Format
449
Figure 139. 7-Bit Addressing Mode
449
Figure 140. 10-Bit Addressing Write Transmit Mode
450
Figure 141. 10-Bit Addressing Read Receive Mode
450
Data Transfer and Acknowledge
451
Figure 142. I C Bus Acknowledge
451
Clock Synchronization
452
Arbitration
452
Figure 143. Clock Synchronization During Arbitration
452
Figure 144. Two Master Arbitration Procedure
452
General Call Addressing
453
Bus Error
453
Address Mask Enable
453
Address Snoop
453
Operation Mode
453
Figure 145. Master Transmitter Timing Diagram
454
Figure 146. Master Receiver Timing Diagram
456
Figure 147. Slave Transmitter Timing Diagram
457
Figure 148. Slave Receiver Timing Diagram
458
Conditions of Holding SCL Line
459
Table 46. Conditions of Holding SCL Line
459
I 2 C Timeout Function
460
PDMA Interface
460
Register Map
461
Table 47. I 2 C Register Map
461
Register Descriptions
462
I 2 C Control Register - I2CCR
462
I 2 C Interrupt Enable Register - I2CIER
464
I 2 C Address Register - I2CADDR
466
I 2 C Status Register - I2CSR
467
C SCL High Period Generation Register - I2CSHPGR
470
I 2 C SCL Low Period Generation Register - I2CSLPGR
471
Table 48. I 2 C Clock Setting Example
471
Figure 149. SCL Timing Diagram
471
C Data Register - I2CDR
472
I 2 C Target Register - I2CTAR
473
I 2 C Address Mask Register - I2CADDMR
474
I 2 C Address Snoop Register - I2CADDSR
475
I 2 C Timeout Register - I2CTOUT
476
21 Serial Peripheral Interface (SPI)
477
Introduction
477
Figure 150. SPI Block Diagram
477
Features
478
Function Descriptions
478
Master Mode
478
Slave Mode
478
SPI Serial Frame Format
479
Table 49. SPI Interface Format Setup
479
Figure 151. SPI Single Byte Transfer Timing Diagram - CPOL = 0, CPHA = 0
479
Figure 152. SPI Continuous Data Transfer Timing Diagram - CPOL = 0, CPHA = 0
480
Figure 153. SPI Single Byte Transfer Timing Diagram - CPOL = 0, CPHA = 1
480
Figure 154. SPI Continuous Transfer Timing Diagram - CPOL = 0, CPHA = 1
481
Figure 155. SPI Single Byte Transfer Timing Diagram - CPOL = 1, CPHA = 0
481
Figure 156. SPI Continuous Transfer Timing Diagram - CPOL = 1, CPHA = 0
482
Figure 157. SPI Single Byte Transfer Timing Diagram - CPOL = 1, CPHA = 1
482
Figure 158. SPI Continuous Transfer Timing Diagram - CPOL = 1, CPHA = 1
482
Status Flags
483
Table 50. SPI Mode Fault Trigger Conditions
484
Table 51. SPI Master Mode SEL Pin Status
484
Figure 159. SPI Multi-Master Slave Environment
484
Register Map
486
Register Descriptions
486
SPI Control Register 0 - SPICR0
486
Table 52. SPI Register Map
486
SPI Control Register 1 - SPICR1
488
SPI Interrupt Enable Register - SPIIER
490
SPI Clock Prescaler Register - SPICPR
491
SPI Data Register - SPIDR
492
SPI Status Register - SPISR
493
SPI FIFO Control Register - SPIFCR
495
SPI FIFO Status Register - SPIFSR
496
SPI FIFO Time out Counter Register - SPIFTOCR
497
22 Universal Synchronous Asynchronous Receiver Transmitter (USART)
498
Introduction
498
Figure 160. USART Block Diagram
498
Features
499
Function Descriptions
500
Serial Data Format
500
Figure 161. USART Serial Data Format
500
Baud Rate Generation
501
Table 53. Baud Rate Deviation Error Calculation - CK_USART = 40 Mhz
501
Figure 162. USART Clock CK_USART and Data Frame Timing
501
Hardware Flow Control
502
Table 54. Baud Rate Deviation Error Calculation - CK_USART = 48 Mhz
502
Figure 163. Hardware Flow Control between 2 Usarts
502
Figure 164. USART RTS Flow Control
503
Figure 165. USART CTS Flow Control
503
Irda
504
Figure 166. Irda Modulation and Demodulation
504
RS485 Mode
506
Figure 167. USART I/O and Irda Block Diagram
506
Figure 168. RS485 Interface and Waveform
507
Synchronous Master Mode
509
Figure 169. USART Synchronous Transmission Example
509
Figure 170. 8-Bit Format USART Synchronous Waveform
510
Interrupts and Status
511
PDMA Interface
511
Register Map
511
Table 55. USART Register Map
511
Register Descriptions
512
USART Data Register - USRDR
512
USART Control Register - USRCR
513
USART FIFO Control Register - USRFCR
515
USART Interrupt Enable Register - USRIER
516
USART Status & Interrupt Flag Register - USRSIFR
518
USART Timing Parameter Register - USRTPR
520
USART Irda Control Register - Irdacr
521
USART RS485 Control Register - RS485CR
522
USART Synchronous Control Register - SYNCR
523
USART Divider Latch Register - USRDLR
524
USART Test Register - USRTSTR
525
23 Universal Asynchronous Receiver Transmitter (UART)
526
Introduction
526
Figure 171. UART Block Diagram
526
Features
527
Function Descriptions
527
Serial Data Format
527
Figure 172. UART Serial Data Format
527
Baud Rate Generation
528
Table 56. Baud Rate Deviation Error Calculation - CK_UART = 40 Mhz
528
Figure 173. UART Clock CK_UART and Data Frame Timing
528
Interrupts and Status
529
PDMA Interface
529
Table 57. Baud Rate Deviation Error Calculation - CK_UART = 48 Mhz
529
Register Map
530
Register Descriptions
530
UART Data Register - URDR
530
Table 58. UART Register Map
530
UART Control Register - URCR
531
UART Interrupt Enable Register - URIER
533
UART Status & Interrupt Flag Register - URSIFR
534
UART Divider Latch Register - URDLR
536
UART Test Register - URTSTR
537
24 Smart Card Interface (SCI)
538
Introduction
538
Figure 174. SCI Block Diagram
538
Features
539
Functional Descriptions
539
Elementary Time Unit Counter
539
Table 59. DI Field Based DI Encoded Decimal Values
540
Table 60. FI Field Based F Encoded Decimal Values
540
Table 61. Possible ETU Values Obtained with the Fi/DI Ratio
540
Guard Time Counter
541
Figure 175. Character Frame and Compensation Mode
541
Waiting Time Counter
542
Figure 176. Guard Time Duration
542
Card Clock and Data Selection
543
Card Detection
543
Figure 177. Character and Block Waiting Time Duration - CWT and BWT
543
SCI Data Transfer Mode
544
Figure 178. SCI Card Detection Diagram
544
Interrupt Generator
546
Figure 179. SCI Interrupt Structure
546
PDMA Interface
547
Register Map
547
Table 62. SCI Register Map
547
Register Descriptions
548
SCI Control Register - CR
548
SCI Status Register - SR
550
SCI Contact Control Register - CCR
552
SCI Elementary Time Unit Register - ETUR
553
SCI Guard Time Register - GTR
554
SCI Waiting Time Register - WTR
555
SCI Interrupt Enable Register - IER
556
SCI Interrupt Pending Register - IPR
558
SCI Transmit Buffer - TXB
560
SCI Receive Buffer - RXB
560
SCI Prescaler Register - PSCR
561
25 USB Device Controller (USB)
562
Introduction
562
Features
562
Figure 180. USB Block Diagram
562
Functional Descriptions
563
Endpoints
563
Ep-Sram
563
Table 63. Endpoint Characteristics
563
Table 64. USB Data Types and Buffer Size
563
Serial Interface Engine - SIE
564
Double-Buffering
564
Figure 181. Endpoint Buffer Allocation Example
564
Figure 182. Double-Buffering Operation Example
565
Suspend Mode and Wake-Up
566
Remote Wake-Up
566
Register Map
566
Table 65. USB Register Map
566
Register Descriptions
568
USB Control and Status Register - USBCSR
568
Table 66. Resume Event Detection
569
USB Interrupt Enable Register - USBIER
570
USB Interrupt Status Register - USBISR
571
USB Frame Count Register - USBFCR
573
USB Device Address Register - USBDEVA
574
USB Endpoint 0 Control and Status Register - USBEP0CSR
575
USB Endpoint 0 Interrupt Enable Register - USBEP0IER
576
USB Endpoint 0 Interrupt Status Register - USBEP0ISR
578
USB Endpoint 0 Transfer Count Register - USBEP0TCR
579
USB Endpoint 0 Configuration Register - USBEP0CFGR
580
USB Endpoint 1 ~ 3 Control and Status Register - Usbepncsr, N = 1 ~ 3
581
USB Endpoint 1 ~ 3 Interrupt Enable Register - Usbepnier, N = 1 ~ 3
582
USB Endpoint 1 ~ 3 Interrupt Status Register - Usbepnisr, N = 1 ~ 3
583
USB Endpoint 1 ~ 3 Transfer Count Register - Usbepntcr, N = 1 ~ 3
584
USB Endpoint 1 ~ 3 Configuration Register - Usbepncfgr, N = 1 ~ 3
585
USB Endpoint 4 ~ 7 Control and Status Register - Usbepncsr, N = 4 ~ 7
586
USB Endpoint 4 ~ 7 Interrupt Enable Register - Usbepnier, N = 4 ~ 7
589
USB Endpoint 4 ~ 7 Interrupt Status Register - Usbepnisr, N = 4 ~ 7
590
USB Endpoint 4 ~ 7 Transfer Count Register - Usbepntcr, N = 4 ~ 7
591
USB Endpoint 4 ~ 7 Configuration Register - Usbepncfgr, N = 4 ~ 7
592
26 Peripheral Direct Memory Access (PDMA)
593
Introduction
593
Features
593
Figure 183. PDMA Block Diagram
593
Functional Description
594
AHB Master
594
PDMA Channel
594
PDMA Request Mapping
594
Table 67. PDMA Channel Assignments
595
Figure 184. PDMA Request Mapping Architecture
595
Channel Transfer
596
Channel Priority
596
Figure 185. PDMA Channel Arbitration and Scheduling Example
596
Transfer Request
597
Address Mode
597
Auto-Reload
597
Table 68. PDMA Address Modes
597
Transfer Interrupt
598
Register Map
598
Table 69. PDMA Register Map
598
Register Descriptions
600
PDMA Channel N Control Register - Pdmachncr, N = 0 ~ 5
600
PDMA Channel N Source Address Register - Pdmachnsadr, N = 0 ~ 5
602
PDMA Channel N Destination Address Register - Pdmachndadr, N=0~5
603
PDMA Channel N Transfer Size Register - Pdmachntsr, N = 0 ~ 5
604
PDMA Channel N Current Transfer Size Register - Pdmachnctsr, N=0~5
605
PDMA Interrupt Status Register - PDMAISR
606
PDMA Interrupt Status Clear Register - PDMAISCR
607
PDMA Interrupt Enable Register - PDMAIER
609
27 Extend Bus Interface (EBI)
610
Introduction
610
Features
610
Function Descriptions
611
Figure 186. EBI Block Diagram
611
Figure 187. EBI Non-Multiplexed 8-Bit Data, 8-Bit Address Read Operation
612
Figure 188. EBI Non-Multiplexed 8-Bit Data, 8-Bit Address Write Operation
612
Non-Multiplexed 8-Bit Data 8-Bit Address Mode
612
Figure 189. EBI Non-Multiplexed 16-Bit Data, N-Bit Address Read Operation
613
Figure 190. EBI Non-Multiplexed 16-Bit Data, N-Bit Address Write Operation
613
Non-Multiplexed 16-Bit Data N-Bit Address Mode
613
Figure 191. an EBI Address Latch Setup Diagram
614
Figure 192. EBI Multiplexed 16-Bit Data, 16-Bit Address Read Operation
614
Multiplexed 16-Bit Data, 16-Bit Address Mode
614
Figure 193. EBI Multiplexed 16-Bit Data, 16-Bit Address Write Operation
615
Figure 194. EBI Multiplexed 8-Bit Data, 20-Bit Address Read Operation
615
Multiplexed 8-Bit Data, 20-Bit Address Mode
615
Bus Turn-Around and Idle Cycles
616
Figure 195. EBI Multiplexed 8-Bit Data, 20-Bit Address Write Operation
616
Write Buffer and EBI Status
616
AHB Transaction Width Conversion
617
Figure 196. EBI Inserts an IDLE Cycle between Transactions in the same Bank (NOIDLE = 0)
617
Figure 197. EBI De-Asserts an IDLE Cycle between Transactions in the same Bank (NOIDLE = 1)
617
Table 70. EBI Maps AHB Transactions Width to External Device Transactions
618
Table 71. EBI Maps AHB Transactions Width to External Device Transactions Width
618
EBI Bank Access
619
Figure 198. EBI Bank Memory Map
619
PDMA Request
620
Register Map
620
Register Descriptions
620
EBI Control Register - EBICR
620
Table 72. EBI Register Map
620
EBI Status Register - EBISR
622
EBI Address Timing Register - EBIATR
623
EBI Read Timing Register - EBIRTR
624
EBI Write Timing Register - EBIWTR
625
EBI Parity Register - EBIPR
626
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Holtek HT32F52352 Manualline (12 pages)
MCU
Brand:
Holtek
| Category:
Microcontrollers
| Size: 0 MB
Table of Contents
Boot Configuration
7
Debug Management
8
Printed Circuit Board
9
Component Position
9
Reference Material
11
Limitation of Liability
12
Governing Law
12
HOLTEK HT32F52352 Firmware Manual (7 pages)
RF Module Generic Development Board Programming
Brand:
HOLTEK
| Category:
Microcontrollers
| Size: 3 MB
Table of Contents
Overview
1
BCE-GENTRX8-001 Programming Setup
2
BCE-GENTRX32-001 Programming Setup
4
Points to Note
6
Reference Material
6
Version and Modification Information
6
Conclusion
6
Limitation of Liability
7
Governing Law
7
Disclaimer
7
Update of Disclaimer
7
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