Instruction Flow; Instruction Queue And Dispatch Unit; Branch Processing Unit (Bpu) - IBM PowerPC 750GX User Manual

User's Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor

1.2.1 Instruction Flow

As shown in Figure 1-1, 750GX Microprocessor Block Diagram, on page 25, the 750GX instruction control
unit provides centralized control of instruction flow to the execution units. The instruction unit contains a
sequential instruction fetch (Ifetch), 6-entry instruction queue (IQ), dispatch unit, and BPU. It determines the
address of the next instruction to be fetched based on information from the sequential instruction fetcher and
from the BPU. See Chapter 6, Instruction Timing, on page 209 for more information.
The sequential instruction fetcher loads instructions from the instruction cache into the instruction queue. The
BPU extracts branch instructions from the sequential instruction fetcher. Branch instructions that cannot be
resolved immediately are predicted using either 750GX-specific dynamic branch prediction or the architec-
ture-defined static branch prediction.
Branch instructions that do not update the LR or CTR are removed from (folded out of) the instruction stream.
Instruction fetching continues along the predicted path of the branch instruction.
Instructions issued to execution units beyond a predicted branch can be executed but are not retired until the
branch is resolved. If branch prediction is incorrect, the completion unit flushes all instructions fetched on the
predicted path, and instruction fetching resumes along the correct path.

1.2.1.1 Instruction Queue and Dispatch Unit

The instruction queue (IQ), shown in Figure 1-1 on page 25, holds as many as six instructions and loads up to
four instructions from the instruction cache during a single-processor clock cycle. The instruction fetcher
continuously attempts to load as many instructions as there were vacancies created in the IQ in the previous
clock cycle. All instructions except branches are dispatched to their respective execution units from the
bottom two positions in the instruction queue (IQ0 and IQ1) at a maximum rate of two instructions per cycle.
Reservation stations are provided for the IU1, IU2, FPU, LSU, and SRU for dispatched instructions. The
dispatch unit checks for source and destination register dependencies, allocates rename buffers, determines
whether a position is available in the completion queue, and inhibits subsequent instruction dispatching if
these resources are not available.
Branch instructions can be detected, decoded, and predicted from anywhere in the instruction queue. For a
more detailed discussion of instruction dispatch, see Section 6.6.1, Branch, Dispatch, and Completion-Unit
Resource Requirements, on page 237.

1.2.1.2 Branch Processing Unit (BPU)

The BPU receives branch instructions from the sequential instruction fetcher and performs CR lookahead
operations on conditional branches to resolve them early, achieving the effect of a zero-cycle branch in many
cases.
Unconditional branch instructions and conditional branch instructions in which the condition is known can be
resolved immediately. For unresolved conditional branch instructions, the branch path is predicted using
either the architecture-defined static branch prediction or 750GX-specific dynamic branch prediction.
Dynamic branch prediction is enabled if the BHT bit in Hardware-Implementation-Dependent Register 0 is set
(HID0[BHT] = 1).
When a prediction is made, instruction fetching, dispatching, and execution continue along the predicted
path, but instructions cannot be retired and write results back to architected registers until the prediction is
determined to be correct (resolved). When a prediction is incorrect, the instructions from the incorrect path
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