Page 1 Title Page PPC440x5 CPU Core User’s Manual Preliminary SA14-2613-02 September 12, 2002...
Page 2 IBM product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary.
Page 3: Table Of Contents
User’s Manual Preliminary PPC440x5 CPU Core Contents Figures ..........................15 Tables ..........................19 About This Book ......................23 1. Overview ........................27 1.1 PPC440x5 Features ........................27 1.2 The PPC440x5 as a PowerPC Implementation ................29 1.3 PPC440x5 Organization ........................30 1.3.1 Superscalar Instruction Unit ....................
Page 4 User’s Manual PPC440x5 CPU Core Preliminary 2.3.2 Allocated Instruction Class ..................... 54 2.3.3 Preserved Instruction Class ....................55 2.3.4 Reserved Instruction Class ....................56 2.4 Implemented Instruction Set Summary ................... 56 2.4.1 Integer Instructions ........................ 57 2.4.1.1 Integer Storage Access Instructions ................57 2.4.1.2 Integer Arithmetic Instructions ..................
Page 5 User’s Manual Preliminary PPC440x5 CPU Core 2.10 Synchronization ..........................82 2.10.1 Context Synchronization ...................... 82 2.10.2 Execution Synchronization ....................83 2.10.3 Storage Ordering and Synchronization ................84 3. Initialization ....................... 85 3.1 PPC440x5 Core State After Reset ....................85 3.2 Reset Types ..........................89 3.3 Reset Sources ..........................
Page 6 User’s Manual PPC440x5 CPU Core Preliminary 5.1 MMU Overview ..........................133 5.1.1 Support for PowerPC Book-E MMU Architecture ..............133 5.2 Translation Lookaside Buffer ......................134 5.3 Page Identification ......................... 138 5.3.1 Virtual Address Formation ....................138 5.3.2 Address Space Identifier Convention ................... 138 5.3.3 TLB Match Process ......................
Page 7 User’s Manual Preliminary PPC440x5 CPU Core 6.4.4 Critical Save/Restore Register 0 (CSRR0) ................168 6.4.5 Critical Save/Restore Register 1 (CSRR1) ................168 6.4.6 Machine Check Save/Restore Register 0 (MCSRR0) ............169 6.4.7 Machine Check Save/Restore Register 1 (MCSRR1) ............169 6.4.8 Data Exception Address Register (DEAR) ................
Page 8 User’s Manual PPC440x5 CPU Core Preliminary 7.4 Watchdog Timer ..........................213 7.5 Timer Control Register (TCR) ....................... 215 7.6 Timer Status Register (TSR) ......................216 7.7 Freezing the Timer Facilities ......................217 7.8 Selection of the Timer Clock Source ..................... 217 8.
Page 9 User’s Manual Preliminary PPC440x5 CPU Core 9.3 Pseudocode ..........................251 9.3.1 Operator Precedence ......................253 9.4 Register Usage ..........................253 9.5 Alphabetical Instruction Listing ...................... 254 add ............................255 addc............................256 adde ............................257 addi............................258 addic............................259 addic............................260 addis............................
Page 10 User’s Manual PPC440x5 CPU Core Preliminary icbt ............................. 314 iccci............................316 icread............................317 isel ............................. 319 isync ............................320 lbz .............................. 321 lbzu ............................322 lbzux ............................323 lbzx ............................324 lha.............................. 325 lhau............................326 lhaux ............................327 lhax ............................328 lhbrx............................
Page 11 User’s Manual Preliminary PPC440x5 CPU Core mtspr ............................370 mulchw ............................373 mulchwu ............................ 374 mulhhw ............................375 mulhhwu ............................ 376 mulhw ............................377 mulhwu ............................378 mullhw ............................379 mullhwu ............................. 380 mulli ............................381 mullw ............................382 nand ............................383 neg ............................
Page 12 User’s Manual PPC440x5 CPU Core Preliminary stwu ............................426 stwux ............................427 stwx ............................428 subf............................429 subfc ............................430 subfe............................431 subfic ............................432 subfme............................433 subfze ............................434 tlbre............................435 tlbsx ............................437 tlbsync ............................438 tlbwe ............................439 tw ...............................
Page 13 User’s Manual Preliminary PPC440x5 CPU Core ICDBDR............................. 491 ICDBTRH ..........................492 ICDBTRL ........................... 493 INV0–INV3 ..........................494 ITV0–ITV3 ..........................495 IVLIM ............................496 IVOR0–IVOR15......................... 497 IVPR ............................498 LR.............................. 499 MCSR............................500 MCSRR0 ........................... 501 MCSRR1 ........................... 502 MMUCR............................. 503 MSR ............................
Page 14 User’s Manual PPC440x5 CPU Core Preliminary Index ..........................571 Revision Log ........................ 589 ppc440x5TOC.fm. Page 14 of 583 September 12, 2002...
Page 15: Figures
User’s Manual Preliminary PPC440x5 CPU Core Figures Figure 1-1. PPC440 Core Block Diagram ....................30 Figure 2-1. User Programming Model Registers ..................48 Figure 2-2. Supervisor Programming Model Registers ................49 Figure 2-3. Link Register (LR) ........................67 Figure 2-4.
Page 16 User’s Manual PPC440x5 CPU Core Preliminary Figure 6-3. Save/Restore Register 1 (SRR1) ..................168 Figure 6-4. Critical Save/Restore Register 0 (CSRR0) ................168 Figure 6-5. Critical Save/Restore Register 1 (CSRR1) ................169 Figure 6-6. Machine Check Save/Restore Register 0 (MCSRR0) ............169 Figure 0-1.
Page 17 User’s Manual Preliminary PPC440x5 CPU Core Figure 10-14. Data Cache Debug Tag Register Low (DCDBTRL) ............. 479 Figure 10-15. Data Exception Address Register (DEAR) ................480 Figure 10-16. Decrementer (DEC) ......................481 Figure 10-17. Decrementer Auto-Reload (DECAR) ................... 482 Figure 10-18. Data Cache Normal Victim Registers (DNV0–DNV3) ............483 Figure 10-19.
Page 18 User’s Manual PPC440x5 CPU Core Preliminary Figure A-2. B Instruction Format ......................522 Figure A-3. SC Instruction Format ......................522 Figure A-4. D Instruction Format ......................522 Figure A-5. X Instruction Format ......................523 Figure A-6. XL Instruction Format ......................524 Figure A-7. XFX Instruction Format ......................524 Figure A-8.
Page 19: Tables
User’s Manual Preliminary PPC440x5 CPU Core Tables Table 2-1. Data Operand Definitions ....................... 40 Table 2-2. Alignment Effects for Storage Access Instructions ..............40 Table 2-3. Register Categories ....................... 50 Table 2-4. Instruction Categories ......................57 Table 2-5. Integer Storage Access Instructions ..................58 Table 2-6.
Page 20 User’s Manual PPC440x5 CPU Core Preliminary Table 5-4. Access Control Applied to Cache Management Instructions ..........144 Table 6-1. Interrupt Types Associated with each IVOR .................171 Table 6-2. Interrupt and Exception Types ....................175 Table 7-1. Fixed Interval Timer Period Selection ...................212 Table 7-2.
Page 21 User’s Manual Preliminary PPC440x5 CPU Core Table 9-31. Extended Mnemonics for tw ....................441 Table 9-32. Extended Mnemonics for twi ....................444 Table 10-1. Register Categories ......................452 Table 10-2. Special Purpose Registers Sorted by SPR Number ............454 Table 10-3.
Page 22 User’s Manual PPC440x5 CPU Core Preliminary ppc440x5LOT.fm. Page 22 of 583 September 12, 2002...
Page 23: About This Book
About This Book This user’s manual provides the architectural overview, programming model, and detailed information about the instruction set, registers, and other facilities of the IBM™ Book-E Enhanced PowerPC™ 440x5 (PPC440x5™) 32-bit embedded controller core. The PPC440x5 embedded controller core features: •...
Page 24 User’s Manual PPC440x5 CPU Core Preliminary Contents, on page v. Figures, on page xi. Tables, on page xiii. Index, on page 571. Notation The manual uses the following notational conventions: • Active low signals are shown with an overbar (Active_Low) •...
Page 25: Related Publications
The following book describes the Book-E Enhanced PowerPC Architecture: • Book E: PowerPC Architecture Enhanced for Embedded Applications (www.chips.ibm.com/techlib/products/powerpc/manuals/) The following CD-ROM contains publications describing the IBM PowerPC 400 family of embedded control- PowerPC PPC440x5 User’s Manual, and application and technical notes. lers, including this manual • I BM PowerPC Embedded Processor Solutions (Order Number SC09-3032) preface.fm.
Page 26 User’s Manual PPC440x5 CPU Core Preliminary preface.fm. Page 26 of 589 September 12, 2002...
Page 27: Overview
In addition, the PPC440x5 core is a member of the PowerPC 400 Series of advanced embedded processors cores, which is supported by the PowerPC Embedded Tools Program. In this program, IBM and many third- party vendors offer a full range of robust development tools for embedded applications. Among these are compilers, debuggers, real-time operating systems, and logic analyzers.
Page 28 User’s Manual PPC440x5 CPU Core Preliminary • 9-port (6-read, 3-write) 32x32-bit General Purpose Register (GPR) ﬁle • Hardware support for all CPU misaligned accesses • Full support for both big and little endian byte ordering • Extensive power management designed into core for maximum performance/power efﬁciency •...
Page 29: The Ppc440X5 As A Powerpc Implementation
– Fixed Interval Timer (FIT) – Watchdog Timer with critical interrupt and/or auto-reset • Multiple core Interfaces deﬁned by the IBM CoreConnect on-chip system architecture • PLB interfaces • Three independent 128-bit interfaces for instruction reads, data reads, and data writes •...
Page 30: Ppc440X5 Organization
User’s Manual PPC440x5 CPU Core Preliminary 1.3 PPC440x5 Organization The PPC440x5 core includes a seven-stage pipelined PowerPC core, which consists of a three stage, dual- issue instruction fetch and decode unit with attached branch unit, together with three independent, 4-stage pipelines for complex integer, simple integer, and load/store operations, respectively.
Page 31: Execution Pipelines
See Chapter 4, “Instruction and Data Caches,” for detailed information about the instruc- tion and data cache controllers. The cache controllers connect to the PLB for connection to the IBM CoreConnect system-on-a-chip environ- ment. 1.3.3.1 Instruction Cache Controller (ICC) The ICC delivers two instructions per cycle to the instruction unit of the PPC440x5 core.
Page 32: Data Cache Controller (Dcc)
User’s Manual PPC440x5 CPU Core Preliminary The ICC supports cache line locking, at either an 8-line or 16-line granularity, depending on cache size (16- line for 32KB, 8-line for 8KB and 16KB). In addition, the notion of a “transient” portion of the cache is...
Page 33 These attributes can be used to control various system- level behaviors, such as instruction compression using IBM CodePack technology. They can also be config- ured to control whether data cache lines are allocated upon a store miss, and whether accesses to a given page should use the “normal”...
Page 34: Timers
The debug modes, events, controls, and interfaces provide a powerful combination of debug facilities for hardware development tools, such as the RISCWatch™ debugger from IBM. A brief overview of the debug modes and development tool support are provided below. Chapter 8, “Debug Facilities,”...
Page 35: Development Tool Support
The RISCTrace™ feature of RISCWatch is an example of a development tool that uses the real-time trace capability of the PPC440x5. 1.4 Core Interfaces Several interfaces to the PPC440x5 core support the IBM CoreConnect on-chip system architecture, which simplifies the attachment of on-chip devices. These interfaces include: • Processor local bus (PLB) •...
Page 36: Processor Local Bus (Plb)
The frequency of each PLB interface can be independently specified, allowing an IBM CoreConnect system in which the interfaces are not all connected as part of the same PLB and in which each PLB subsystem operates at its own frequency. Each PLB inter- face frequency can be configured to any value such that the ratio of the processor core frequency to the PLB (core:PLB) is n:1, n:2, or n:3, where n is any integer greater than or equal to the denominator of the ratio.
Page 37: Jtag Port
The PPC440x5 JTAG port is enhanced to support the attachment of a debug tool such as the RISCWatch product from IBM. Through the JTAG test access port, and using the debug facilities designed into the PPC440x5 core, a debug workstation can single-step the processor and interrogate internal processor state to facilitate hardware and software debugging.
Page 38 User’s Manual PPC440x5 CPU Core Preliminary overview.fm. Page 38 of 589 September 12, 2002...
Page 39: Programming Model
User’s Manual Preliminary PPC440x5 CPU Core 2. Programming Model The programming model of the PPC440x5 core describes how the following features and operations of the core appear to programmers: • Storage addressing (including data types and byte ordering), starting on page 39 •...
Page 40: Table 2-1. Data Operand Definitions
User’s Manual PPC440x5 CPU Core Preliminary Data storage operands for storage access instructions have the following characteristics. Table 2-1. Data Operand Deﬁnitions Storage Access Instruction Operand Addr[28:31] if aligned Type Length Byte (or String) 8 bits 0bxxxx Halfword 2 bytes...
Page 41: Effective Address Calculation
User’s Manual Preliminary PPC440x5 CPU Core Similarly, the TLB management instructions access page operands, and—as determined by the page size— the associated low-order effective address bits are ignored during the execution of these instructions. Instruction storage operands, on the other hand, are always four bytes long, and the effective addresses calculated by Branch instructions are therefore always word-aligned.
Page 42: Byte Ordering
User’s Manual PPC440x5 CPU Core Preliminary The 14-bit BD field is concatenated on the right with 0b00, sign-extended, and then added to either the address of the branch instruction if AA=0, or to 0 if AA=1; the low-order 32 bits of the sum form the effec- tive address of the next instruction.
Page 43: Structure Mapping Examples
This ordering is called big endian because the “big end” (most-significant end) of the scalar, considered as a binary number, comes first in storage. IBM RISC System/6000, IBM System/390, and Motorola 680x0 are examples of computer architectures using this byte ordering.
Page 44: Instruction Byte Ordering
User’s Manual PPC440x5 CPU Core Preliminary Big Endian Mapping s follows (the data is highlighted in the structure mappings). Addresses, The big endian mapping of structure in hexadecimal, are below the data stored at the address. The contents of each byte, as defined in structure s , is shown as a (hexadecimal) number or character (for the string elements).
Page 45: Data Byte Ordering
User’s Manual Preliminary PPC440x5 CPU Core On the other hand, in a little endian mapping the same instruction is arranged with the least-significant byte (LSB) of the instruction word at the lowest-numbered address: 0x00 0x01 0x02 0x03 By the definition of PowerPC Book-E bit numbering, the most-significant byte of an instruction is the byte containing bits 0:7 of the instruction.
Page 46: Byte-Reverse Instructions
User’s Manual PPC440x5 CPU Core Preliminary • For word loads and stores (including load/store multiple), bytes are reversed within the word, for one byte order with respect to the other. • For doubleword loads and stores (AP loads/stores only), bytes are reversed within the doubleword, for one byte order with respect to the other.
Page 47: Registers
User’s Manual Preliminary PPC440x5 CPU Core 2.2 Registers This section provides an overview of the register categories and types provided by the PPC440x5. Detailed descriptions of each of the registers are provided within the chapters covering the functions with which they are associated (for example, the cache control and cache debug registers are described in Instruction and Data Caches on page 95).
Page 48: Figure 2-1. User Programming Model Registers
User’s Manual PPC440x5 CPU Core Preliminary Integer Processing Branch Control General Purpose Condition Register GPR0 Count Register GPR1 GPR2 • Link Register • • GPR31 Processor Control Integer Exception Register SPR General 4–7 SPRG4 Timer SPRG5 Time Base SPRG5 SPRG7...
Page 49: Figure 2-2. Supervisor Programming Model Registers
User’s Manual Preliminary PPC440x5 CPU Core Processor Control Timer Storage Control Machine State Register Time Base Process ID Processor Version Register MMU Control Register Timer Control Register MMUCR Processor ID Register Debug Timer Status Register Debug Status Register Core Conﬁguration Registers...
Page 50: Table 2-3. Register Categories
User’s Manual PPC440x5 CPU Core Preliminary Table 2-3. Register Categories Register Category Register(s) Model and Access Type Page User User Branch Control User DNV0–DNV3 Supervisor DTV0–DTV3 Supervisor DVLIM Supervisor Cache Control INV0–INV3 Supervisor ITV0–ITV3 Supervisor IVLIM Supervisor DCDBTRH, DCDBTRL Supervisor, read-only...
Page 51 User’s Manual Preliminary PPC440x5 CPU Core Table 2-3. Register Categories Register Category Register(s) Model and Access Type Page Supervisor DECAR Supervisor, write-only TBL, TBU User read, Supervisor write Timer Supervisor Supervisor prgmodel.fm. September 12, 2002 Page 51 of 589...
Page 52: Register Types
User’s Manual PPC440x5 CPU Core Preliminary 2.2.1 Register Types There are five register types contained within and/or supported by the PPC440x5 core. Each register type is characterized by the instructions which are used to read and write the registers of that type. The following subsections provide an overview of each of the register types and the instructions associated with them.
Page 53: Machine State Register
User’s Manual Preliminary PPC440x5 CPU Core 2.2.1.4 Machine State Register The Machine State Register (MSR) is a register of its own unique type that controls important chip functions, such as the enabling or disabling of various interrupt types. mtmsr instruction. The contents of the MSR can be read into The MSR can be written from a GPR using the mfmsr instruction.
Page 54: Allocated Instruction Class
User’s Manual PPC440x5 CPU Core Preliminary • cause a Floating-Point Unavailable interrupt if the instruction is recognized as a ﬂoating-point instruction, but ﬂoating-point processing is disabled; or • cause an Unimplemented Instruction exception type Program interrupt, if the instruction is recognized as a ﬂoating-point instruction and ﬂoating-point processing is enabled, but the instruction is not supported by...
Page 55: Preserved Instruction Class
User’s Manual Preliminary PPC440x5 CPU Core In addition to supporting the defined instructions of PowerPC Book-E, the PPC440x5 also implements a number of instructions which use the allocated instruction opcodes, and thus are not part of the PowerPC Book-E architecture. Table 2-21 on page 63 identifies the allocated instructions that are implemented within the PPC440x5 core.
Page 56: Reserved Instruction Class
User’s Manual PPC440x5 CPU Core Preliminary 2.3.4 Reserved Instruction Class This class of instructions consists of all instruction primary opcodes (and associated extended opcodes, if applicable) which do not belong to either the defined, allocated, or preserved instruction classes. Reserved instructions are available for future versions of PowerPC Book-E architecture. That is, future versions of PowerPC Book-E may define any of these instructions to perform new functions or make them available for implementation-dependent use as allocated instructions.
Page 57: Integer Instructions
User’s Manual Preliminary PPC440x5 CPU Core Table 2-4 summarizes the PPC440x5 instruction set by category. Instructions within each category are described in subsequent sections. Table 2-4. Instruction Categories Category Subcategory Instruction Types Integer Storage Access load, store Integer Arithmetic add, subtract, multiply, divide, negate...
Page 58: Integer Arithmetic Instructions
User’s Manual PPC440x5 CPU Core Preliminary an “indexed” form (in which the address is formed by adding the contents of the RA and RB GPRs) and a “base + displacement” form (in which the address is formed by adding a 16-bit signed immediate value (spec- ified as part of the instruction) to the contents of GPR RA.
Page 59: Integer Logical Instructions
User’s Manual Preliminary PPC440x5 CPU Core 2.4.1.3 Integer Logical Instructions Table 2-7 lists the integer logical instructions in the PPC440x5. See Integer Arithmetic Instructions on page 58 for an explanation of the “[ . ]” syntax. Table 2-7. Integer Logical Instructions...
Page 60: Integer Shift Instructions
User’s Manual PPC440x5 CPU Core Preliminary 2.4.1.7 Integer Shift Instructions Table 2-11 lists the integer shift instructions in the PPC440x5. Note that the shift right algebraic insructions implicitly update the XER[CA] field. See Integer Arithmetic Instructions on page 58 for an explanation of the “[...
Page 61: Condition Register Logical Instructions
User’s Manual Preliminary PPC440x5 CPU Core 2.4.3.1 Condition Register Logical Instructions These instructions perform logical operations on a specified pair of bits in the CR, placing the result in another specified bit. The benefit of these instructions is that they can logically combine the results of several comparison operations without incurring the overhead of conditional branching between each one.
Page 62: Storage Control Instructions
User’s Manual PPC440x5 CPU Core Preliminary Table 2-17 shows the processor synchronization instruction in the PPC440x5. Table 2-17. Processor Synchronization Instruction isync 2.4.4 Storage Control Instructions These instructions manage the instruction and data caches and the TLB of the PPC440x5 core. Instructions are also provided to synchronize and order storage accesses.
Page 63: Storage Synchronization Instructions
PowerPC Book-E architecture identifies as being available for implementation-dependent and/or application-specific purposes. However, all of the allocated instructions which are implemented within the PPC440x5 core are “standard” for IBM’s family of PowerPC embedded controllers, and are not unique to the PPC440x5.
Page 64: Branch Processing
User’s Manual PPC440x5 CPU Core Preliminary 2.5 Branch Processing The four branch instructions provided by PPC440x5 are summarized in Table 2.4.2 on Page 60. In addition, each of these instructions is described in detail in Instruction Set on page 249. The following sections provide additional information on branch addressing, instruction fields, prediction, and registers.
Page 65: Branch Prediction
User’s Manual Preliminary PPC440x5 CPU Core Table 2-22 summarizes the usage of the bits of the BO field. BO[4] is further discussed in Branch Prediction on page 65 Table 2-22. BO Field Deﬁnition BO Bit Description CR Test Control 0 Test CR bit speciﬁed by BI ﬁeld for value speciﬁed by BO[1]...
Page 66: Branch Control Registers
User’s Manual PPC440x5 CPU Core Preliminary The PPC440x5 core combines the static prediction mechanism defined by PowerPC Book-E, together with a dynamic branch prediction mechanism, in order to provide correct branch prediction as often as possible. The dynamic branch prediction mechanism is an implementation optimization, and is not part of the architecture, nor is it visible to the programming model.
Page 67: Count Register (Ctr)
User’s Manual Preliminary PPC440x5 CPU Core When being used as a return address by a bclr instruction, bits 30:31 of the LR are ignored, since all instruc- tion addresses are on word boundaries. Access to the LR is non-privileged. Figure 2-3. Link Register (LR)
Page 68: Figure 2-5. Condition Register (Cr)
User’s Manual PPC440x5 CPU Core Preliminary 11 12 15 16 19 20 23 24 27 28 Figure 2-5. Condition Register (CR) Condition Register Field 0 Condition Register Field 1 8:11 Condition Register Field 2 12:15 Condition Register Field 3 16:19...
Page 69: Table 2-24. Cr Updating Instructions
User’s Manual Preliminary PPC440x5 CPU Core Table 2-24. CR Updating Instructions Processor Storage Auxiliary Integer Control Control Processor CR-Logical Storage Arithmetic Arithmetic Logical Compare Rotate Shift and Register Access Mgmt. and Logical Management macchw. macchws. macchwsu. macchwu. and. add. machhw.
Page 70 User’s Manual PPC440x5 CPU Core Preliminary • Certain forms of various integer instructions (the “.” forms) implicitly update CR[CR0], as do certain forms of the auxiliary processor instructions implemented within the PPC440x5 core. • Auxiliary processor instructions may in general update a speciﬁed CR ﬁeld in an implementation-speci- ﬁed manner.
Page 71: Integer Processing
User’s Manual Preliminary PPC440x5 CPU Core CR Update By Integer Compare Instructions Integer compare instructions update a specified CR field with the result of a comparison of two 32-bit numbers, the first of which is from a GPR and the second of which is either an immediate value or from another GPR.
Page 72: Integer Exception Register (Xer)
User’s Manual PPC440x5 CPU Core Preliminary 2.6.2 Integer Exception Register (XER) The XER records overflow and carry indications from integer arithmetic and shift instructions. It also provides a byte count for string indexed integer storage access instructions (lswx and stswx). Note that the term exception in the name of this register does not refer to exceptions as they relate to interrupts, but rather to the arithmetic exceptions of carry and overflow.
Page 73: Summary Overflow (So) Field
User’s Manual Preliminary PPC440x5 CPU Core Table 2-25. XER[SO,OV] Updating Instructions Processor Con- Integer Arithmetic Auxiliary Processor trol Multiply-Accumu- Negative Multi- Register Man- Subtract Multiply Divide Negate late ply- Accumulate agement macchwo macchws macchwsu macchwu nmacchw addo subfo machhw nmacchws...
Page 74: Overflow (Ov) Field
User’s Manual PPC440x5 CPU Core Preliminary 2.6.2.2 Overﬂow (OV) Field This field is updated by certain integer arithmetic instructions to indicate whether the infinitely precise result of the operation can be represented in 32 bits. For those integer arithmetic instructions that update XER[OV] and produce signed results, XER[OV] = 1 if the result is greater than 2 –...
Page 75: Special Purpose Registers General (Usprg0, Sprg0-Sprg7)
User’s Manual Preliminary PPC440x5 CPU Core • Processor Version Register (PVR) Indicates the specific implementation of a processor • Processor Identiﬁcation Register (PIR) Indicates the specific instance of a processor in a multi-processor system • Core Conﬁguration Register 0 (CCR0) Controls specific processor functions, such as instruction prefetch •...
Page 76: Processor Identification Register (Pir)
User’s Manual PPC440x5 CPU Core Preliminary 11 12 Figure 2-9. Processor Version Register (PVR) 0:11 Owner Identifier Identifies the owner of a core. Implementation-specific value identifying the spe- 12:31 Processor Version Number cific version and use of a processor core within a chip.
Page 77: Figure 2-11. Core Configuration Register 0 (Ccr0)
User’s Manual Preliminary PPC440x5 CPU Core DSTG DTB GDCBT ICSLC 9 10 11 12 15 16 17 18 19 22 23 24 27 28 29 30 31 CRPE DAPUIB GICBT FLSTA ICSLT Figure 2-11. Core Conﬁguration Register 0 (CCR0) Reserved...
Page 78: Core Configuration Register 1 (Ccr1)
User’s Manual PPC440x5 CPU Core Preliminary Force Load/Store Alignment 0 No Alignment exception on integer storage access instructions, regardless of alignment FLSTA See Load and Store Alignment on page 117. 1 An alignment exception occurs on integer storage access instructions if data address is not on an operand boundary.
Page 79: Reset Configuration (Rstcfg)
User’s Manual Preliminary PPC440x5 CPU Core Controls inversion of parity bit recorded for the U Data Cache U-bit Parity Error Insert fields in the data cache. 0 record even parity (normal) DCUPEI 1 record odd parity (simulate parity error) Data Cache Modified-bit Parity Error Insert...
Page 80: User And Supervisor Modes
User’s Manual PPC440x5 CPU Core Preliminary U1 Storage Attribute 0 U1 storage attribute is disabled See Table 5-1 on page 135. 1 U1 storage attribute is enabled U2 Storage Attribute 0 U2 storage attribute is disabled See Table 5-1 on page 135.
Page 81: Privileged Sprs
User’s Manual Preliminary PPC440x5 CPU Core Table 2-27. Privileged Instructions (continued) mfmsr mfspr For any SPR Number with SPRN 5 = 1. See Privileged SPRs on page 81. mtdcr mtmsr mtspr For any SPR Number with SPRN 5 = 1. See Privileged SPRs on page 81.
Page 82: Synchronization
User’s Manual PPC440x5 CPU Core Preliminary The architecture provides two mechanisms for protecting against errant accesses to such “non-well-behaved” memory addresses. The first is the guarded (G) storage attribute, and protects against speculative data accesses. The second is the execute permission mechanism, and protects against speculative instruction fetches.
Page 83: Execution Synchronization
User’s Manual Preliminary PPC440x5 CPU Core fetch and execute the instruction at address XYZ In this sequence, the isync instruction does not guarantee that the XYZ instruction is fetched after the store has occurred to memory. There is no guarantee which XYZ instruction will execute; either the old version or the new (stored) version might.
Page 84: Storage Ordering And Synchronization
User’s Manual PPC440x5 CPU Core Preliminary thought of as being context synchronizing with respect to the MSR[EE] bit, in that it guarantees that subse- quent instructions execute (or are prevented from executing and an interrupt taken) according to the new context of MSR[EE].
Page 85: Initialization
User’s Manual Preliminary PPC440x5 CPU Core 3. Initialization This chapter describes the initial state of the PPC440x5 core after a hardware reset, and contains a descrip- tion of the initialization software required to complete initialization so that the PPC440x5 core can begin executing application code.
Page 86: Table 3-1. Reset Values Of Registers And Other Ppc440X5 Facilities
User’s Manual PPC440x5 CPU Core Preliminary nizing operation (including causing any exceptions which would lead to an interrupt), since a context synchronizing operation will invalidate the shadow TLB entries. Initialization software should consider all other resources within the PPC440x5 core to be undefined after reset, in order for the initialization sequence to be compatible with other PowerPC implementations.
Page 87 User’s Manual Preliminary PPC440x5 CPU Core Table 3-1. Reset Values of Registers and Other PPC440x5 Facilities Resource Field Reset Value Comment Unconditional debug event has not occurred Indicates most recent type of reset as follows: 00 No reset has occurred since this ﬁeld last cleared by software...
Page 88 User’s Manual PPC440x5 CPU Core Preliminary Table 3-1. Reset Values of Registers and Other PPC440x5 Facilities Resource Field Reset Value Comment System-dependent System-dependent System-dependent RSTCFG All RSTCFG fields are specified by core input signals System-dependent System-dependent EPRN System-dependent 0b00 Watchdog Timer reset disabled...
Page 89: Reset Types
User’s Manual Preliminary PPC440x5 CPU Core 3.2 Reset Types The PPC440x5 core supports three types of reset: core, chip, and system. The type of reset is indicated by a set of core input signals. For each type of reset, the core resources are initialized as indicated in Table 3-1 on page 86.
Page 90 User’s Manual PPC440x5 CPU Core Preliminary 2. Invalidate the instruction cache (iccci) 3. Invalidate the data cache (dccci) 4. Synchronize memory accesses (msync) This step forces any data PLB operations that may have been in progress prior to the reset operation to complete, thereby allowing subsequent data accesses to be initiated and completed properly.
Page 91 User’s Manual Preliminary PPC440x5 CPU Core care must be taken during the initialization sequence to prevent any such context synchronizing opera- tions (such as interrupts and the isync instruction) until after this step is completed, and an architected TLB entry has been established in the TLB. Particular care should be taken to avoid store operations, since write permission is disabled upon reset, and an attempt to execute any store operation would result in a Data Storage interrupt, thereby invalidating the shadow TLB entry.
Page 92 User’s Manual PPC440x5 CPU Core Preliminary 11. Initialize interrupt resources 1. Initialize IVPR to specify high-order address of the interrupt handling routines Make sure that the corresponding address region is covered by a TLB entry (or entries) 2. Initialize IVOR0–IVOR15 registers (individual interrupt vector addresses) Make sure that the corresponding addresses are covered by a TLB entry (or entries) Because the low order four bits of IVOR0–IVOR15 are reserved, the values written to those bits are...
Page 93 User’s Manual Preliminary PPC440x5 CPU Core 1. Set MSR[CE] to enable/disable Critical Input and Watchdog Timer interrupts 2. Set MSR[EE] to enable/disable External Input, Decrementer, and Fixed Interval Timer interrupts 3. Set MSR[DE] to enable/disable Debug interrupts 4. Set MSR[ME] to enable/disable Machine Check interrupts...
Page 94 User’s Manual PPC440x5 CPU Core Preliminary init.fm. Page 94 of 589 September 12, 2002...
Page 95: Instruction And Data Caches
The cache controllers interface to the processor local bus (PLB) for connection to the IBM CoreConnect system-on-a-chip environment. Both the data and instruction caches are parity protected against soft errors. If such errors are detected, the CPU will vector to the machine check interrupt handler, where software can take appropriate action.
Page 96: Cache Line Replacement Policy
User’s Manual PPC440x5 CPU Core Preliminary ated with the line that currently resides in that way. The middle-order address bits form an index to select a specific set of the cache, while the five lowest-order address bits form a byte-offset to choose a specific byte (or bytes, depending on the size of the operation) from the 32-byte cache line.
Page 97: Figure 4-1. Instruction Cache Normal Victim Registers (Inv0-Inv3)
User’s Manual Preliminary PPC440x5 CPU Core VNDXA VNDXC 15 16 23 24 VNDXB VNDXD Figure 4-1. Instruction Cache Normal Victim Registers (INV0–INV3) Instruction Cache Transient Victim Registers (ITV0–ITV3) Data Cache Normal Victim Registers (DNV0–DNV3) Data Cache Transient Victim Registers (DTV0–DTV3)
Page 98: Table 4-3. Victim Index Field Selection
User’s Manual PPC440x5 CPU Core Preliminary The size of the victim index fields varies according to the size of the respective cache. Also, which field is used varies according to the type of access, the size of the cache, and the address of the cache line.
Page 99: Cache Locking And Transient Mechanism
User’s Manual Preliminary PPC440x5 CPU Core 4.1.2 Cache Locking and Transient Mechanism Both caches support locking, at a “way” granularity. Any number of ways can be locked, from 0 ways to one less than the total number of ways (64 ways for 32KB and 16KB cache sizes, 32 ways for the 8KB cache size).
Page 100 User’s Manual PPC440x5 CPU Core Preliminary Replacement Policy on page 96, the values of the fields are constrained to lie within the range specified by the NFLOOR field of the corresponding victim limit register, and the last way of the cache (way 31 for the 8KB cache size, way 63 for the 16KB or 32KB cache size).
Page 101 User’s Manual Preliminary PPC440x5 CPU Core block -- 32 bytes), it takes sixteen such dcbt operations (one for each set) before the next way of the ini- tial set will be targeted again. 7. Execute msync and then isync again, to guarantee that all of the dcbt operations have completed and updated the corresponding victim index ﬁelds.
Page 102: Figure 4-3. Cache Locking And Transient Mechanism (Example 1)1
User’s Manual PPC440x5 CPU Core Preliminary Figure 4-3 and Figure 4-4 illustrate two of these examples of the use of the locking and transient mecha- nisms. Other configurations are possible, given the ability to program each of the victim limit fields to different relative values, although some configurations are not necessarily useful or practical.
Page 103: Instruction Cache Controller
User’s Manual Preliminary PPC440x5 CPU Core Figure 4-4. Cache Locking and Transient Mechanism (Example 2) Cache Set n Way w NORMAL LINES Way TCEILING+1 Way TCEILING NORMAL/TRANSIENT LINES Way NFLOOR Way NFLOOR-1 TRANSIENT LINES Way TFLOOR Way TFLOOR-1 LOCKED LINES...
Page 104: Icc Operations
User’s Manual PPC440x5 CPU Core Preliminary The ICC also handles the execution of the PowerPC instruction cache management instructions, for touching (prefetching) or invalidating cache lines, or for flash invalidation of the entire cache. Resources for controlling and debugging the instruction cache operation are also provided.
Page 105: Speculative Prefetch Mechanism
User’s Manual Preliminary PPC440x5 CPU Core the ICC will immediately present the request for the new cache line, such that it may be serviced immediately after the previous cache line read is completed. The ICC never aborts any PLB request once it has been made, except when a processor reset occurs while the PLB request is being made.
Page 106: Instruction Cache Coherency
User’s Manual PPC440x5 CPU Core Preliminary lines beyond the one in progress at the time that the ICC determines that it needs to request a new line will be abandoned. For example, if CCR0[ICSLC] is set to 3, and the ICC is in the middle of receiving the data for the...
Page 107: Instruction Cache Synonyms
User’s Manual Preliminary PPC440x5 CPU Core At this point, software may begin executing the instruction at addr1 and be guaranteed that the new instruc- tion will be recognized. 4.2.3.2 Instruction Cache Synonyms A synonym is a cache line that is associated with the same real address as another cache line that is in the cache array at the same time.
Page 108: Instruction Cache Control And Debug
User’s Manual PPC440x5 CPU Core Preliminary Alternatively, software can execute an iccci instruction, which flash invalidates the entire instruction cache without regard to the addresses with which the cache lines are associated. 4.2.4 Instruction Cache Control and Debug The PPC440x5 core provides various registers and instructions to control instruction cache operation and to help debug instruction cache problems.
Page 109: Figure 4-5. Core Configuration Register 0 (Ccr0)
User’s Manual Preliminary PPC440x5 CPU Core DSTG DTB GDCBT ICSLC 9 10 11 12 15 16 17 18 19 22 23 24 27 28 29 30 31 CRPE DAPUIB GICBT FLSTA ICSLT Figure 4-5. Core Conﬁguration Register 0 (CCR0) Reserved...
Page 110: Core Configuration Register 1 (Ccr1)
User’s Manual PPC440x5 CPU Core Preliminary Force Load/Store Alignment 0 No Alignment exception on integer storage access instructions, regardless of alignment FLSTA See Load and Store Alignment on page 117. 1 An alignment exception occurs on integer storage access instructions if data address is not on an operand boundary.
Page 111: Icbt Operation
User’s Manual Preliminary PPC440x5 CPU Core Data Cache U-bit Parity Error Insert Controls inversion of parity bit recorded for the U 0 record even parity (normal) fields in the data cache. DCUPEI 1 record odd parity (simulate parity error) Data Cache Modified-bit Parity Error Insert...
Page 112: Icread Operation
User’s Manual PPC440x5 CPU Core Preliminary When being used for these latter purposes, it is important that the icbt instruction deliver a deterministic result, namely the guaranteed establishment in the cache of the specified line. Accordingly, the PPC440x5 core provides a field in the CCR0 register that can be used to cause the icbt instruction to operate in this manner.
Page 113: Figure 4-7. Instruction Cache Debug Data Register (Icdbdr)
User’s Manual Preliminary PPC440x5 CPU Core mﬁcdbdr regC # move instruction information into GPR C mﬁcdbtrh regD # move high portion of tag into GPR D mﬁcdbtrl regE # move low portion of tag into GPR E The following figures illustrate the ICDBDR, ICDBTRH, and ICDBTRL.
Page 114: Instruction Cache Parity Operations
User’s Manual PPC440x5 CPU Core Preliminary Translation ID (TID) Disable TID Disable field for the memory page associated 0 TID enable with the cache line read by icread. 1 TID disable TID field portion of the virtual address associated 24:31 Translation ID with the cache line read by icread.
Page 115: Data Cache Controller
User’s Manual Preliminary PPC440x5 CPU Core There are 10 parity bits stored in the RAM cells of each instruction cache line. Two of those bits hold the parity for the tag information, and the remaining 8 bits hold the parity for each of the 8 32-bit instruction words in the line.
Page 116: Dcc Operations
User’s Manual PPC440x5 CPU Core Preliminary support direct attachment to 32-bit and 64-bit PLB subsystems, as well as 128-bit PLB subsystems. The DCC handles frequency synchronization between the PPC440x5 core and the PLB, and can operate at any ratio of n :1, n :2, and n :3, where n is an integer greater than the corresponding denominator.
Page 117: Load And Store Alignment
User’s Manual Preliminary PPC440x5 CPU Core Once a data cache line read request has been made, the entire line read will be performed and the line will be written into the data cache, regardless of whether or not the instruction stream branches (or is interrupted) away from the instruction which prompted the initial line read request.
Page 118: Load Operations
User’s Manual PPC440x5 CPU Core Preliminary The load and store string and multiple instructions are performed using one memory access for each four bytes, unless and until an access would cross an aligned quadword boundary. The access that would cross...
Page 119: Store Operations
User’s Manual Preliminary PPC440x5 CPU Core 4.3.1.3 Store Operations The processing of store instructions in the DCC is affected by several factors, including the caching inhibited (I), write-through (W), and guarded (G) storage attributes, as well as whether or not the allocation of data cache lines is enabled for cacheable store misses.
Page 120 User’s Manual PPC440x5 CPU Core Preliminary A given sequence of two store operations may only be gathered together if the targeted bytes are contained within the same aligned quadword of memory, and if they are contiguous with respect to each other. Subse- quent store operations may continue to be gathered with the previously gathered sequence, subject to the same two rules (same aligned quadword and contiguous with the collection of previously gathered bytes).
Page 121: Line Flush Operations
User’s Manual Preliminary PPC440x5 CPU Core Table 4-5 summarizes how the various storage attributes and other circumstances affect the DCC behavior on store accesses. Table 4-5. Data Cache Behavior on Store Accesses Store Access Attributes DCC Actions Caching Write Guarded...
Page 122: Data Read Plb Interface Requests
User’s Manual PPC440x5 CPU Core Preliminary set instead of just the one corresponding dirty bit). When a data cache line is flushed, the type of request made to the data write PLB interface depends upon which dirty bits associated with the line are set, and the state of the CCR1[FFF] bit.
Page 123: Data Write Plb Interface Requests
User’s Manual Preliminary PPC440x5 CPU Core 4.3.1.6 Data Write PLB Interface Requests When a PLB write request results from a data cache line flush, the specific type and size of the request is as described in Line Flush Operations on page 121.
Page 124: Storage Access Ordering
User’s Manual PPC440x5 CPU Core Preliminary 4.3.1.7 Storage Access Ordering In general, the DCC can perform load and store operations out-of-order with respect to the instruction stream. That is, the memory accesses associated with a sequence of load and store instructions may be performed in memory in an order different from that implied by the order of the instructions.
Page 125: Data Cache Control And Debug
User’s Manual Preliminary PPC440x5 CPU Core 4.3.3 Data Cache Control and Debug The PPC440x5 core provides various registers and instructions to control data cache operation and to help debug data cache problems. 4.3.3.1 Data Cache Management and Debug Instruction Summary For detailed descriptions of the instructions summarized in this section, see Instruction Set on page 249 In the instruction descriptions, the term “block”...
Page 126: Core Configuration Register 0 (Ccr0)
User’s Manual PPC440x5 CPU Core Preliminary 4.3.3.2 Core Conﬁguration Register 0 (CCR0) The CCR0 register controls the behavior of the dcbt instruction, the handling of misaligned memory accesses, and the store gathering mechanism. The CCR0 register also controls various other functions within the PPC440x5 core that are unrelated to the data cache.
Page 127: Dcread Operation
User’s Manual Preliminary PPC440x5 CPU Core the specified cache line in the data cache (assuming that a TLB entry for the referenced memory page exists and has read permission, and that the caching inhibited storage attribute is not set). The cache line fill associ- ated with such a guaranteed dcbt will occur regardless of any potential instruction execution-stalling circum- stances within the DCC.
Page 128: Figure 4-10. Data Cache Debug Tag Register High (Dcdbtrh)
User’s Manual PPC440x5 CPU Core Preliminary The following figures illustrate the DCDBTRH and DCDBTRL. TERA 23 24 25 27 28 Figure 4-10. Data Cache Debug Tag Register High (DCDBTRH) Bits 0:23 of the lower 32 bits of the 36-bit real...
Page 129: Data Cache Parity Operations
User’s Manual Preliminary PPC440x5 CPU Core 4.3.3.6 Data Cache Parity Operations The data cache contains parity bits and multi-hit detection hardware to protect against soft data errors. Both the data cache tags and data are protected. Data cache lines consist of a tag field, 256 bits of data, 4 modi- fied (dirty) bits, 4 user attribute (U) bits, and 39 parity bits.
Page 130: Simulating Data Cache Parity Errors For Software Testing
User’s Manual PPC440x5 CPU Core Preliminary MCSR[DCSP] and MCSR[DCFP] indicate what type of data cache operation caused a parity exception. One of the two bits will be set if a parity error is detected in the data cache, along with MCSR[MCS]. See Machine Check Interrupts on page 161.
Page 131 User’s Manual Preliminary PPC440x5 CPU Core If the CCR1[DCMPEI] bit is set, the parity for any modified (dirty) bits that are written, either during the process of a line fill or by execution of a store instruction or dcbz , is set to odd parity. If the CCR1[FFF] bit is also set in addition to CCR1[DCMPEI], then the parity for all four modified (dirty) bits is set to odd parity.
Page 132 User’s Manual PPC440x5 CPU Core Preliminary cache.fm. Page 132 of 589 September 12, 2002...
Page 133: Memory Management
User’s Manual Preliminary PPC440x5 CPU Core 5. Memory Management The PPC440x5 supports a uniform, 4 gigabyte (GB) effective address (EA) space, and a 64GB (36-bit) real address (RA) space. The PPC440x5 memory management unit (MMU) performs address translation between effective and real addresses, as well as protection functions. With appropriate system software, the MMU supports: •...
Page 134: Translation Lookaside Buffer
User’s Manual PPC440x5 CPU Core Preliminary • Memory coherence required (M) storage attribute Because the PPC440x5 does not provide hardware support for multiprocessor coherence, the memory coherence required storage attribute has no effect. If a TLB entry is created with M=1, then any memory...
Page 135: Table 5-1. Tlb Entry Fields
User’s Manual Preliminary PPC440x5 CPU Core Maintenance of TLB entries is under software control. System software determines the TLB entry replace- ment strategy and the format and use of any page table information. A TLB entry contains all of the informa- tion required to identify the page, to specify the address translation, to control the access permissions, and to designate the storage attributes.
Page 136 User’s Manual PPC440x5 CPU Core Preliminary Table 5-1. TLB Entry Fields (continued) Field Description Word Address Translation Fields Real Page Number (variable size, from 4 - 22 bits) Bits 0:n–1 of the RPN field are used to replace bits 0:n–1 of the effective address to produce a portion of the real address for the storage access (where n = 32–log...
Page 137 User’s Manual Preliminary PPC440x5 CPU Core Table 5-1. TLB Entry Fields (continued) Field Description Word Memory Coherence Required (1 bit) See Memory Coherence Required (M) on page 146. The page is not memory coherence required. The page is memory coherence required.
Page 138: Page Identification
User’s Manual PPC440x5 CPU Core Preliminary Table 5-1. TLB Entry Fields (continued) Field Description Word Supervisor State Read Enable (1 bit) See Read Access on page 143. Load operations and the dcbt, dcbtst, dcbst, dcbf, icbt, and icbi instructions are not per- mitted from this page when MSR[PR]=0 and will cause a Read Access Control exception.
Page 139: Tlb Match Process
User’s Manual Preliminary PPC440x5 CPU Core space, allowing user mode programs running with MSR[IS,DS] set to 1 to access them (system library routines, for example, which may be shared by multiple user mode and/or supervisor mode programs). System-level code wishing to use these areas would have to first set the corresponding MSR[IS,DS] field in order to use the application-level TLB entries, or there would have to be alternative system-level TLB entries set up.
Page 140: Address Translation
User’s Manual PPC440x5 CPU Core Preliminary Figure 5-1 illustrates the criteria for a virtual address to match a specific TLB entry, while Table 5-2 defines the page sizes associated with each SIZE field value, and the associated comparison of the effective address to the EPN field.
Page 141: Figure 5-2. Effective-To-Real Address Translation Flow
User’s Manual Preliminary PPC440x5 CPU Core The Real Page Number (RPN) and Extended Real Page Number (ERPN) fields of the matching TLB entry provide the page number portion of the real address. Let n=32–log (page size in bytes) where page size is specified by the SIZE field of the matching TLB entry.
Page 142: Access Control
User’s Manual PPC440x5 CPU Core Preliminary Table 5-3. Page Size and Real Address Formation SIZE Page Size RPN bits required to be 0 Real Address 0b0000 none || EA 0:21 22:31 0b0001 || EA 20:21 0:19 20:31 0b0010 16KB || EA...
Page 143: Read Access
User’s Manual Preliminary PPC440x5 CPU Core store operation is attempted in user mode to a page for which the UW access control bit is 0, then a Write Access Control exception occurs. If the instruction is an stswx with string length 0, then no interrupt is taken and no operation is performed (see Access Control Applied to Cache Management Instructions on page 143).
Page 144: Table 5-4. Access Control Applied To Cache Management Instructions
User’s Manual PPC440x5 CPU Core Preliminary • dcbz instructions are treated as stores with respect to access control since they actually change the data in a cache block. As such, they can cause Write Access Control exception type Data Storage interrupts.
Page 145: Storage Attributes
User’s Manual Preliminary PPC440x5 CPU Core Table 5-4. Access Control Applied to Cache Management Instructions Read Write Protection Protection Instruction Violation Violation Exception? Exception? icbt iccci dcbt, dcbtst, or icbt may cause a Read Access Control exception but will not result in a Data Storage interrupt 5.6 Storage Attributes...
Page 146: Memory Coherence Required (M)
User’s Manual PPC440x5 CPU Core Preliminary See Instruction and Data Caches on page 95 for more information on the handling of accesses to caching inhibited storage. 5.6.3 Memory Coherence Required (M) The memory coherence required (M) storage attribute is defined by the architecture to support cache and memory coherency within multiprocessor shared memory systems.
Page 147: User-Definable (U0-U3)
As an example, one of the user-definable storage attributes could be used to enable code compession using the IBM CodePack core, if this function is included within a specific implementation incorporating the PPC440x5 core.
Page 148: Memory Management Unit Control Register (Mmucr)
User’s Manual PPC440x5 CPU Core Preliminary 5.7.1 Memory Management Unit Control Register (MMUCR) mtspr , and can be read into a GPR using mfspr . In addition, the The MMUCR is written from a GPR using MMUCR[STID] is updated with the TID field of the selected TLB entry when a tlbre instruction is executed.
Page 149 User’s Manual Preliminary PPC440x5 CPU Core Store Without Allocate (SWOA) Field Performance for certain applications can be affected by the allocation of cache lines on store misses. If the store accesses for a particular application are distributed sparsely in memory, and if the data is typically not re-used after having been stored, then performance may be improved by avoiding the latency and bus band- width associated with filling the entire cache line containing the bytes being stored.
Page 150 User’s Manual PPC440x5 CPU Core Preliminary program to remove a locked line from the cache. The locking and unlocking of cache lines is generally a supervisor mode function, as the supervisor has access to the various mechanisms which control the cache locking mechanism (e.g., the Data Cache Victim Limit (DVLIM) and Instruction Cache Victim Limit (IVLIM)
Page 151: Process Id (Pid)
User’s Manual Preliminary PPC440x5 CPU Core Search Translation ID (STID) Field The STID field is used by the tlbsx[.] instruction to designate the process identifier value to be compared with the TID field of the TLB entries. For instruction fetch and data storage accesses and cache management operations, the TID field of the TLB entries is compared with the value in the PID register (see Process ID (PID) on page 151).
Page 152: Tlb Management Instructions
User’s Manual PPC440x5 CPU Core Preliminary The instruction shadow TLB (ITLB) contains four entries, while the data shadow TLB (DTLB) contains eight. There is no latency associated with accessing the shadow TLB arrays, and instruction execution continues in a pipelined fashion as long as the requested address is found in the shadow TLB. If the requested address is not found in the shadow TLB, the instruction fetch or data storage access is automatically stalled while the address is looked up in the UTLB.
Page 153: Tlb Search Instruction (Tlbsx[.])
User’s Manual Preliminary PPC440x5 CPU Core is the Data Exception Address Register (DEAR), which provides the exception-causing address for Data TLB Error and Data Storage interrupts. Finally, the Exception Syndrome Register (ESR) provides bits to differen- tiate amongst the various exception types which may cause a particular interrupt type. See Chapter 6, “Inter- rupts and Exceptions.”...
Page 154: Tlb Sync Instruction (Tlbsync)
User’s Manual PPC440x5 CPU Core Preliminary TLB Word 0 (WS=0) SIZE TPAR TLB Word 1 (WS=1) 23 24 21 22 27 28 PAR1 ERPN TLB Word 2 (WS=2) PAR2 U1 U2 U3 UX UW UR SX SW SR Figure 5-5. TLB Entry Word Deﬁnitions 5.9.3 TLB Sync Instruction (tlbsync)
Page 155: Tlb Parity Operations
User’s Manual Preliminary PPC440x5 CPU Core Execute, Read and Write Access Control exceptions may be used to allow software to maintain reference and change information for a TLB entry and for its associated memory page. The following description explains one way in which system software can maintain such reference and change information.
Page 156: Simulating Tlb Parity Errors For Software Testing
User’s Manual PPC440x5 CPU Core Preliminary 2. MSR[ME] = 1, so the CPU vectors to the machine check handler (i.e takes the machine check interrupt) and resets the MSR[ME] bit. Note that even though the parity error causes an asynchronous interrupt, that interrupt is guaranteed to be taken before the tlbre instruction completes if the CCR0[PRE] (Parity Recoverability Enable) is set, and so the target register (RT) of the tlbre will not be updated.
Page 157 User’s Manual Preliminary PPC440x5 CPU Core tlbwe Rs,Ra,2 ; write some data to the TLB with bad parity isync ; wait for the tlbwe(s) to ﬁnish mtspr CCR1, Rz ; Reset CCR1[MMUPEI] isync ; wait for the CCR1 context to update tlbre RT,RA,WS ;...
Page 158 User’s Manual PPC440x5 CPU Core Preliminary mmu.fm. Page 158 of 589 September 12, 2002...
Page 159: Interrupts And Exceptions
User’s Manual Preliminary PPC440x5 CPU Core 6. Interrupts and Exceptions This chapter begins by defining the terminology and classification of interrupts and exceptions in “Overview” and “Interrupt Classes”. Interrupt Processing on page 162 explains in general how interrupts are processed, including the require- ments for partial execution of instructions.
Page 160: Synchronous, Precise Interrupts
User’s Manual PPC440x5 CPU Core Preliminary Synchronous, precise interrupts are those that precisely indicate the address of the instruction causing the exception that generated the interrupt; or, for certain synchronous, precise interrupt types, the address of the immediately following instruction.
Page 161: Critical And Non-Critical Interrupts
User’s Manual Preliminary PPC440x5 CPU Core • No instruction following the instruction addressed by SRR0 or CSRR0 has executed. The only synchronous, imprecise interrupts in the PPC440x5 core are the “special cases” of “delayed” inter- rupts, which can result when certain kinds of exceptions occur while the corresponding interrupt type is disabled.
Page 162: Interrupt Processing
User’s Manual PPC440x5 CPU Core Preliminary properly be classified as either synchronous or asynchronous, nor as precise or imprecise. They also do not belong to either the critical or the non-critical interrupt class, but instead have associated with them a unique pair of save/restore registers, Machine Check Save/Restore Registers 0/1 (MCSRR0/1).
Page 163 User’s Manual Preliminary PPC440x5 CPU Core Interrupt processing consists of saving a small part of the processor state in certain registers, identifying the cause of the interrupt in another register, and continuing execution at the corresponding interrupt vector loca- tion. When an exception exists and the corresponding interrupt type is enabled, the following actions are performed, in order: 1.
Page 164: Partially Executed Instructions
User’s Manual PPC440x5 CPU Core Preliminary 6.3.1 Partially Executed Instructions In general, the architecture permits load and store instructions to be partially executed, interrupted, and then to be restarted from the beginning upon return from the interrupt. In order to guarantee that a particular load...
Page 165: Interrupt Processing Registers
User’s Manual Preliminary PPC440x5 CPU Core Decrementer Fixed-Interval Timer Watchdog Timer Debug (Unconditional Debug Event) 2. Unaligned elementary load or store, or any load or store multiple or string: All of the above listed under item 1, plus the following:...
Page 166 User’s Manual PPC440x5 CPU Core Preliminary Critical Interrupt Enable 0 Critical Input and Watchdog Timer interrupts are disabled. 1 Critical Input and Watchdog Timer interrupts are enabled. Reserved External Interrupt Enable 0 External Input, Decrementer, and Fixed Interval Timer interrupts are disabled.
Page 167: Save/Restore Register 0 (Srr0)
User’s Manual Preliminary PPC440x5 CPU Core 28:31 Reserved 6.4.2 Save/Restore Register 0 (SRR0) SRR0 is an SPR that is used to save machine state on non-critical interrupts, and to restore machine state when an rﬁ is executed. When a non-critical interrupt occurs, SRR0 is set to an address associated with the rﬁ...
Page 168: Critical Save/Restore Register 0 (Csrr0)
User’s Manual PPC440x5 CPU Core Preliminary 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Figure 6-3. Save/Restore Register 1 (SRR1) Copy of the MSR at the time of a non-critical inter- 0:31 rupt.
Page 169: Machine Check Save/Restore Register 0 (Mcsrr0)
User’s Manual Preliminary PPC440x5 CPU Core Programming Note: An MSR bit that is reserved may be altered by rfci, consistent with the value being restored from CSRR1. mtspr , and can be read into a GPR using mfspr . CSRR1 can be written from a GPR using 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Figure 6-5.
Page 170: Data Exception Address Register (Dear)
User’s Manual PPC440x5 CPU Core Preliminary Programming Note: An MSR bit that is reserved may be altered by rfmci, consistent with the value being restored from MCSRR1. mtspr , and can be read into a GPR using mfspr . MCSRR1 can be written from a GPR using 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Figure 0-1.
Page 171: Interrupt Vector Prefix Register (Ivpr)
User’s Manual Preliminary PPC440x5 CPU Core Figure 6-8 shows the IVOR field definitions, while Table 6-1 identifies the specfic IVOR register associated with each interrupt type. 15 16 27 28 Figure 6-8. Interrupt Vector Offset Registers (IVOR0–IVOR15) 0:15 Reserved 16:27...
Page 172: Exception Syndrome Register (Esr)
User’s Manual PPC440x5 CPU Core Preliminary 15 16 Figure 6-9. Interrupt Vector Preﬁx Register (IVPR) 0:15 Interrupt Vector Prefix 16:31 Reserved 6.4.11 Exception Syndrome Register (ESR) The ESR provides a syndrome to differentiate between the different kinds of exceptions that can generate the same interrupt type.
Page 173 User’s Manual Preliminary PPC440x5 CPU Core Floating Point Operation 0 Exception was not caused by a ﬂoating point instruction. 1 Exception was caused by a ﬂoating point instruction. Store Operation 0 Exception was not caused by a store-type storage access or cache management instruction.
Page 174: Machine Check Status Register (Mcsr)
User’s Manual PPC440x5 CPU Core Preliminary This is an implementation-dependent field of the ESR and is not part of the PowerPC Book-E Archi- Program Interrupt—Condition Register Field tecture. If ESR[PCRE]=1, this field indicates which CR field 29:31 PCRF was to be updated by the floating-point instruction This field is only defined for a Floating-Point which caused the exception.
Page 175: Interrupt Definitions
User’s Manual Preliminary PPC440x5 CPU Core Instruction Cache Parity Error 0 Exception not caused by I-cache parity error 1 Exception caused by I-cache parity error Set if and only If the DCU parity error was dis- Data Cache Search Parity Error covered during a DCU Search operation.
Page 176: Table 6-2. Interrupt And Exception Types
User’s Manual PPC440x5 CPU Core Preliminary Table 6-2. Interrupt and Exception Types IVOR Interrupt Type Exception Type (See Note 4) Illegal Instruction Privileged Instruction PPR,[AP] Trap IVOR6 Program FP,[PIE],[PCRE] FP Enabled {PCMP,PCRF} AP Enabled Unimplemented Op PUO,[FP,AP] IVOR7 FP Unavailable...
Page 177 User’s Manual Preliminary PPC440x5 CPU Core Table 6-2. Interrupt and Exception Types IVOR Interrupt Type Exception Type (See Note 4) Table Notes 1. Although it is not speciﬁed as part of Book E, it is common for system implementations to provide, as part of the interrupt controller, independent mask and status bits for the various sources of Critical Input and External Input interrupts.
Page 178: Critical Input Interrupt
User’s Manual PPC440x5 CPU Core Preliminary 6.5.1 Critical Input Interrupt A Critical Input interrupt occurs when no higher priority exception exists, a Critical Input exception is presented to the interrupt mechanism, and MSR[CE] = 1. A Critical Input exception is caused by the activa- tion of an asynchronous input to the PPC440x5 core.
Page 179 User’s Manual Preliminary PPC440x5 CPU Core tion, regardless of the state of the MSR[ME] bit. If MSR[ME] is 1 when the Instruction Machine Check exception is presented to the interrupt mechanism, then execution of the instruction associated with the exception will be sup- pressed, a Machine Check interrupt will occur, and the interrupt processing registers will be updated as described on Page 179.
Page 180 User’s Manual PPC440x5 CPU Core Preliminary Machine Check Save/Restore Register 1 (MCSRR1) Set to the contents of the MSR at the time of the interrupt. Machine State Register (MSR) All MSR bits set to 0. Exception Syndrome Register (ESR) Set to 1 for an Instruction Machine Check exception; otherwise left unchanged.
Page 181: Data Storage Interrupt
User’s Manual Preliminary PPC440x5 CPU Core See Machine Check Interrupts on page 161 for more information on the handling of Machine Check interrupts within the PPC440x5 core. Programming Note: If a Instruction Synchronous Machine Check exception occurs (i.e. an error occurs on the PLB transfer that is intended to ﬁll a line in the instruction cache, any data associated with the exception will not be placed into the instruction cache.
Page 182 User’s Manual PPC440x5 CPU Core Preliminary instructions not with the execution of instructions. Data Storage exceptions and Data TLB Miss exceptions are associated with the execution of instruction cache management instructions, as well as with the execution of load, store, and data cache management instructions.
Page 183 User’s Manual Preliminary PPC440x5 CPU Core • dcbtst For all other instructions, if a Data Storage exception occurs, then execution of the instruction causing the exception is suppressed, a Data Storage interrupt is generated, the interrupt processing registers are updated as indicated below (all registers not listed are unchanged), and instruction execution resumes at address IVPR[IVP] || IVOR2[IVO] || 0b0000.
Page 184: Instruction Storage Interrupt
User’s Manual PPC440x5 CPU Core Preliminary Set to 1 if the instruction causing the interrupt is an auxiliary processor load or store; otherwise set to 0. Set to 1 if the instruction caused a Byte Ordering exception; otherwise set to 0. Note...
Page 185: External Input Interrupt
User’s Manual Preliminary PPC440x5 CPU Core Machine State Register (MSR) CE, ME, DE Unchanged. All other MSR bits set to 0. Exception Syndrome Register (ESR) Set to 0. Unchanged. All other defined ESR bits are set to 0. 6.5.5 External Input Interrupt An External Input interrupt occurs when no higher priority exception exists, an External Input exception is presented to the interrupt mechanism, and MSR[EE] = 1.
Page 186 User’s Manual PPC440x5 CPU Core Preliminary • An integer load or store instruction that references a data storage operand that is not aligned on an oper- and-sized boundary, when CCR0[FLSTA] is 1. Load and store multiple instructions are considered to ref- erence word operands, and hence word-alignment is required for the target address of these instructions when CCR0[FLSTA] is 1.
Page 187: Program Interrupt
User’s Manual Preliminary PPC440x5 CPU Core Exception Syndrome Register (ESR) Set to 1 if the instruction causing the interrupt is a floating-point load or store; otherwise set to 0. Set to 1 if the instruction causing the interrupt is a store, dcbz, or dcbi instruction;...
Page 188 User’s Manual PPC440x5 CPU Core Preliminary exception will cause a Debug interrupt to occur, rather than a Program interrupt. See Chapter 8, “Debug Facilities” for more information on Trap debug events. Unimplemented Operation exception An Unimplemented Operation exception occurs when execution is attempted of any of the following kinds of instructions: •...
Page 189 User’s Manual Preliminary PPC440x5 CPU Core was already being presented to the interrupt mechanism at the time MSR[FE0,FE1] was changed from 0 to a non-zero value, SRR0 is set to the address of the instruction that would have executed after the MSR-changing instruction. If the instruction which set...
Page 190: Floating-Point Unavailable Interrupt
User’s Manual PPC440x5 CPU Core Preliminary Programming Note: The ESR[PCRE,PCMP,PCRF] ﬁelds are provided to assist the Program interrupt handler with the emulation of part of the function of the various ﬂoating-point CR-updating instructions, when any of these instructions cause a precise (“non-delayed”) Floating-Point Enabled exception type Program interrupt.
Page 191: Auxiliary Processor Unavailable Interrupt
User’s Manual Preliminary PPC440x5 CPU Core Save/Restore Register 1 (SRR1) Set to the contents of the MSR at the time of the interrupt. Machine State Register (MSR) CE, ME, DE Unchanged. All other MSR bits set to 0. 6.5.10 Auxiliary Processor Unavailable Interrupt...
Page 192: Fixed-Interval Timer Interrupt
User’s Manual PPC440x5 CPU Core Preliminary Save/Restore Register 1 (SRR1) Set to the contents of the MSR at the time of the interrupt. Machine State Register (MSR) CE, ME, DE Unchanged. All other MSR bits set to 0. Programming Note: Software is responsible for clearing the Decrementer exception status by writing to TSR[DIS], prior to reenabling MSR[EE], in order to avoid another, redundant Decrementer interrupt.
Page 193: Data Tlb Error Interrupt
User’s Manual Preliminary PPC440x5 CPU Core Critical Save/Restore Register 0 (CSRR0) Set to the effective address of the next instruction to be executed. Critical Save/Restore Register 1 (CSRR1) Set to the contents of the MSR at the time of the interrupt.
Page 194: Instruction Tlb Error Interrupt
User’s Manual PPC440x5 CPU Core Preliminary Save/Restore Register 0 (SRR0) Set to the effective address of the instruction causing the Data TLB Error interrupt. Save/Restore Register 1 (SRR1) Set to the contents of the MSR at the time of the interrupt.
Page 195: Debug Interrupt
User’s Manual Preliminary PPC440x5 CPU Core When an Instruction TLB Error interrupt occurs, the processor suppresses the execution of the instruction causing the Instruction TLB Miss exception, the interrupt processing registers are updated as indicated below (all registers not listed are unchanged), and instruction execution resumes at address IVPR[IVP] || IVOR14[IVO] || 0b0000.
Page 196 User’s Manual PPC440x5 CPU Core Preliminary specified by the various debug facility registers. This exception can occur regardless of debug mode, and regardless of the value of MSR[DE]. Branch Taken (BRT) exception A BRT Debug exception occurs when BRT debug events are enabled (DBCR0[BRT]=1) and execution is attempted of a branch instruction for which the branch conditions are met.
Page 197 User’s Manual Preliminary PPC440x5 CPU Core Programming Note: It is a programming error for software to enable internal debug mode (by setting DBCR0[IDM] to 1) while Debug exceptions are already present in the DBSR. Software must ﬁrst clear all DBSR Debug exception status (that is, all ﬁelds except IDE, MRR, IAC12ATS, and...
Page 198 User’s Manual PPC440x5 CPU Core Preliminary Since the ICMP Debug exception does not suppress the execution of the instruction causing the exception, but rather allows it to complete before causing the interrupt, the behavior of the interrupt is different in the special case where the instruction causing the ICMP Debug exception is itself setting MSR[DE] to 0.
Page 199: Interrupt Ordering And Masking
User’s Manual Preliminary PPC440x5 CPU Core 6.6 Interrupt Ordering and Masking It is possible for multiple exceptions to exist simultaneously, each of which could cause the generation of an interrupt. Furthermore, the PowerPC Book-E architecture does not provide for the generation of more than one interrupt of the same class (critical or non-critical) at a time.
Page 200 User’s Manual PPC440x5 CPU Core Preliminary This prevents any asynchronous interrupts, as well as (in the case of MSR[DE]) any Debug interrupts (which include both synchronous and asynchronous types). • Branching (or sequential execution) to addresses not mapped by the TLB, or mapped without execute access permission This prevents Instruction Storage and Instruction TLB Error interrupts.
Page 201: Interrupt Order
User’s Manual Preliminary PPC440x5 CPU Core interrupt may have occurred from within a non-critical class interrupt handler, prior to the non-critical class interrupt handler having saved SRR0 and SRR1. Therefore, within the critical class interrupt handler, both pairs of save/restore registers may contain data that is necessary to the system software.
Page 202: Exception Priorities
User’s Manual PPC440x5 CPU Core Preliminary 6.7 Exception Priorities PowerPC Book-E requires all synchronous (precise and imprecise) interrupts to be reported in program order, as implied by the sequential execution model. The one exception to this rule is the case of multiple synchronous imprecise interrupts.
Page 203: Exception Priorities For Floating-Point Load And Store Instructions
User’s Manual Preliminary PPC440x5 CPU Core Only applies to the defined 64-bit load, store, and cache management instructions, which are not recog- nized by the PPC440x5 core. 5. Program (Privileged Instruction) Only applies to the dcbi instruction, and only occurs if MSR[PR]=1.
Page 204: Exception Priorities For Floating-Point Instructions (Other)
User’s Manual PPC440x5 CPU Core Preliminary 4. Program (Illegal Instruction exception) This exception will occur if no auxiliary processor unit is attached to the PPC440x5 core, or if the particu- lar allocated load or store instruction is not recognized by the attached auxiliary processor.
Page 205: Exception Priorities For Allocated Instructions (Other)
User’s Manual Preliminary PPC440x5 CPU Core This exception will occur if an attached floating-point unit recognizes and supports the instruction, float- ing-point instruction processing is enabled (MSR[FP]=1), and the instruction sets FPSCR[FEX] to 1. 8. Debug (ICMP exception) 6.7.5 Exception Priorities for Allocated Instructions (Other)
Page 206: Exception Priorities For Trap Instructions
User’s Manual PPC440x5 CPU Core Preliminary instructions that are implemented within the PPC440x5 core. This list also covers the defined 64-bit privileged instructions, the tlbiva instruction, and the mfapidi instruction, all of which are not implemented by the PPC440x5 core.
Page 207: Exception Priorities For Branch Instructions
User’s Manual Preliminary PPC440x5 CPU Core 6.7.9 Exception Priorities for Branch Instructions The following list identifies the priority order of the exception types that may occur within the PPC440x5 core as the result of the attempted execution of a branch instruction.
Page 208: Exception Priorities For All Other Instructions
User’s Manual PPC440x5 CPU Core Preliminary 4. Program (Illegal Instruction exception) Applies to all reserved instruction opcodes except the reserved-nop instruction opcodes. 5. Debug (ICMP exception) Only applies to the reserved-nop instruction opcodes. 6.7.13 Exception Priorities for All Other Instructions...
Page 209: Timer Facilities
User’s Manual Preliminary PPC440x5 CPU Core 7. Timer Facilities The PPC440x5 provides four timer facilities: a time base, a Decrementer (DEC), a Fixed Interval Timer (FIT), and a Watchdog Timer. These facilities, which share the same source clock frequency, can support: •...
Page 210: Reading The Time Base
User’s Manual PPC440x5 CPU Core Preliminary Software access to TBU and TBL is non-privileged for read but privileged for write, and hence different SPR numbers are used for reading than for writing. TBU and TBL are written using mtspr and read using mfspr .
Page 211: Decrementer (Dec)
User’s Manual Preliminary PPC440x5 CPU Core Ry, lower Rz, 0 # set GPR Rz to 0 mtspr TBL,Rz # force TBL to 0 (thereby preventing wrap into TBU) mtspr TBU,Rx # set TBU to initial value mtspr TBL,Ry # set TBL to initial value 7.2 Decrementer (DEC)
Page 212: Fixed Interval Timer (Fit)
User’s Manual PPC440x5 CPU Core Preliminary Figure 7-5. Decrementer Auto-Reload (DECAR) Copied to DEC at next time base clock when 0:31 Decrementer auto-reload value DEC = 1 and auto-reload is enabled (TCR[ARE] = 1). mtspr to force the DEC to 0 does not cause a Decrementer exception and thus does not cause Using TSR[DIS] to be set.
Page 213: Watchdog Timer
User’s Manual Preliminary PPC440x5 CPU Core Table 7-1. Fixed Interval Timer Period Selection (continued) Period Period TCR[FP] Time Base Bit (Time Base Clocks) (400 Mhz Clock) 0b11 clocks 83.9 ms When a Fixed Interval Timer exception occurs, the exception status is recorded by setting the Fixed interval Timer Interrupt Status (FIS) field of the TSR to 1.
Page 214: Table 7-3. Watchdog Timer Exception Behavior
User’s Manual PPC440x5 CPU Core Preliminary avoid another Watchdog Timer interrupt due to the same exception (unless TCR[WIE] is cleared instead). Watchdog Timer Interrupt on page 192 provides more information on the handling of Watchdog Timer inter- rupts. If TSR[WIS] is already 1 at the time of the next Watchdog Timer exception, then the action to take depends on the value of the Watchdog Reset Control (TRC) field of the TCR.
Page 215: Timer Control Register (Tcr)
User’s Manual Preliminary PPC440x5 CPU Core Figure 7-6 illustrates the sequence of Watchdog Timer events which occurs according to this typical system usage. Watchdog Timer exception disabled; next exception sets TSR[ENW] so subsequent exception will set TSR[WIS]. Watchdog Timer exception Exception enabled;...
Page 216: Timer Status Register (Tsr)
User’s Manual PPC440x5 CPU Core Preliminary FP FIE 0 1 2 3 4 5 6 7 8 9 10 Figure 7-7. Timer Control Register (TCR) Watchdog Timer Period 00 2 time base clocks 01 2 time base clocks 10 2...
Page 217: Freezing The Timer Facilities
User’s Manual Preliminary PPC440x5 CPU Core 0 1 2 3 4 5 6 Figure 7-8. Timer Status Register (TSR) Enable Next Watchdog Timer Exception 0 Action on next Watchdog Timer exception is to set TSR[ENW] = 1. 1 Action on next Watchdog Timer exception is governed by TSR[WIS].
Page 218 User’s Manual PPC440x5 CPU Core Preliminary timers.fm. Page 218 of 589 September 12, 2002...
Page 219: Debug Facilities
JTAG debug port is typically provided by a debug tool such as the RISC- Watch™ development tool from IBM. A trace port, which enables the tracing of code running in real time, is also provided.
Page 220: External Debug Mode
User’s Manual PPC440x5 CPU Core Preliminary page 159 for a description of the MSR and Debug interrupts). When a Debug interrupt occurs, special debugger software at the interrupt handler can check processor status and other conditions related to the debug event, as well as alter processor resources using all of the instructions defined for the PPC440x5.
Page 221: Trace Debug Mode
User’s Manual Preliminary PPC440x5 CPU Core Debug wait mode is enabled by setting both MSR[DWE] and the debug wait mode enable within the JTAG controller to 1. Since MSR[DWE] is automatically cleared upon any interrupt, debug wait mode is temporarily disabled upon an interrupt, and then can be automatically re-enabled when returning from the interrupt due to the restoration of the MSR value upon the execution of an rfi, rfci, or rfmci instruction.
Page 222: Instruction Address Compare (Iac) Debug Event
User’s Manual PPC440x5 CPU Core Preliminary Table 8-1. Debug Events Event Description Instruction Complete (ICMP) Caused by the successful completion of the execution of any instruction. Interrupt (IRPT) Caused by the generation of an interrupt. Caused by the assertion of an unconditional debug event request from the JTAG inter- Unconditional (UDE) face to the PPC440x5 core.
Page 223 User’s Manual Preliminary PPC440x5 CPU Core Note that the IAC range auto-toggle mechanism can “switch” the IAC range mode from inclusive to exclusive, and vice-versa. See IAC Range Mode Auto-Toggle Field on page 224. • Range exclusive comparison mode (DBCR1[IAC12M/IAC34M] = 0b11)
Page 224 User’s Manual PPC440x5 CPU Core Preliminary matches the IAC conditions and is in virtual address space 1 (MSR[IS] = 1). Note that in these latter two modes, in which the virtual address space of the instruction is considered, it is not the entire virtual address which is considered.
Page 225: Iac Debug Event Processing
User’s Manual Preliminary PPC440x5 CPU Core status fields is summarized in Table 8-2 Table 8-2. IAC Range Mode Auto-Toggle Summary DBCR1 DBCR1 DBSR IAC Mode IAC12M/IAC34M IAC12AT/IAC34AT IAC12ATS/IAC34ATS 0b10 — Range Inclusive 0b10 Range Inclusive 0b10 Range Exclusive 0b11 —...
Page 226: Data Address Compare (Dac) Debug Event
User’s Manual PPC440x5 CPU Core Preliminary interrupt has occurred imprecisely. On the other hand, if the IAC mode is set to either range inclusive or range exclusive mode, then IAC debug events cannot occur when operating in internal debug mode with MSR[DE] = 0, unless external debug mode and/or debug wait mode is also enabled.
Page 227 User’s Manual Preliminary PPC440x5 CPU Core DAC Mode Field DBCR2[DAC12M] controls the comparison mode for the DAC1 and DAC2 events. There are four comparison modes supported by the PPC440x5: • Exact comparison mode (DBCR2[DAC12M] = 0b00) In this mode, the data address is compared to the value in the corresponding DAC register, and the DAC event occurs only if the comparison is an exact match.
Page 228 User’s Manual PPC440x5 CPU Core Preliminary When the data address falls outside the specified range, either one or both of the DAC debug event bits corresponding to the operation type (read or write) will be set in the DBSR, as determined by which of the corresponding two DAC event enable bits are set in DBCR0.
Page 229: Dac Debug Event Processing
User’s Manual Preliminary PPC440x5 CPU Core 8.3.2.2 DAC Debug Event Processing The behavior of the PPC440x5 upon a DAC debug event depends on the setting of DBCR2[DAC12A]. This field of DBCR2 controls whether DAC debug events are processed in a synchronous (DBCR2[DAC12A] = 0) or an asynchronous (DBCR2[DAC12A] = 1) fashion.
Page 230: Dac Debug Events Applied To Instructions That Result In Multiple Storage Accesses
User’s Manual PPC440x5 CPU Core Preliminary counter will contain the address of that instruction, and that instruction’s execution will have been suppressed. Conversely, if the DAC debug event is processed after the completion of the instruction causing the event, then the program counter will contain the address of some instruction after the one which caused the event.
Page 231: Data Value Compare (Dvc) Debug Event
User’s Manual Preliminary PPC440x5 CPU Core dcbst, dcbf dcbst and dcbf instructions are considered “loads” with respect to storage access control, since they do not change the contents of a given storage location. They may merely cause the data at that storage location to be moved from the data cache out to memory. However, in a debug environment, the fact that these instructions may lead to write operations on the external interface is typically the event of interest.
Page 232: Dvc Debug Event Fields
User’s Manual PPC440x5 CPU Core Preliminary Event on page 226 describes the DAC conditions. In addition to the DAC conditions, there are two DVC regis- ters on the PPC440x5, DVC1 and DVC2. The DVC registers can be used to specify two independent, 4-byte data values, which are selectively compared against the data being accessed by a given load, store, or cache management instruction.
Page 233: Dvc Debug Event Processing
User’s Manual Preliminary PPC440x5 CPU Core In this mode, at least one data byte lane that is enabled by a DVC byte enable field must be being accessed and must match the corresponding byte data value in the corresponding DVC1 or DVC2 register.
Page 234: Branch Taken (Brt) Debug Event
User’s Manual PPC440x5 CPU Core Preliminary lswx, stswx DVC debug events do not occur for lswx or stswx instructions with a length of 0 (XER[TBC] = 0), since these instructions do not actually access storage. 8.3.4 Branch Taken (BRT) Debug Event...
Page 235: Return (Ret) Debug Event
User’s Manual Preliminary PPC440x5 CPU Core 8.3.6 Return (RET) Debug Event RET debug events occur when RET debug events are enabled (DBCR0[RET] = 1) and execution is attempted of a return (rfi, rfci, or rfmci) instruction. When operating in external debug mode or debug wait mode, the occurrence of a RET debug event is recorded in DBSR[RET] and causes the instruction execution to be suppressed.
Page 236: Interrupt (Irpt) Debug Event
User’s Manual PPC440x5 CPU Core Preliminary that there is a special case of MSR[DE] = 1 at the time of the execution of the instruction causing the ICMP debug event, but that instruction itself sets MSR[DE] to 0. This special case is described in more detail in Debug Interrupt on page 195, in the subsection on the setting of CSRR0.
Page 237: Unconditional Debug Event (Ude)
User’s Manual Preliminary PPC440x5 CPU Core 8.3.9 Unconditional Debug Event (UDE) UDE debug events occur when a debug tool asserts the unconditional debug event request via the JTAG interface. The UDE debug event is the only event which does not have a corresponding enable field in DBCR0.
Page 238: Debug Reset
User’s Manual PPC440x5 CPU Core Preliminary Table 8-3. Debug Event Summary (continued) External Debug Internal Debug Events Debug Wait Debug TRAP ICMP IRPT Mode Mode Mode Disabled Disabled Enabled Note 2 Note 3 Note 1 Disabled Disabled Disabled — Note 4 Table Notes 1.
Page 239: Debug Control Register 0 (Dbcr0)
User’s Manual Preliminary PPC440x5 CPU Core changing any of the debug facility register ﬁelds related to the DAC and/or DVC debug events, software must execute an msync instruction before making the changes, to ensure that all storage accesses complete using the old context of these register ﬁelds.
Page 240: Debug Control Register 1 (Dbcr1)
User’s Manual PPC440x5 CPU Core Preliminary IAC 2 Debug Event 0 Disable IAC 2 debug event. IAC2 1 Enable IAC 2 debug event. IAC 3 Debug Event 0 Disable IAC 3 debug event. IAC3 1 Enable IAC 3 debug event.
Page 241 User’s Manual Preliminary PPC440x5 CPU Core IAC 1 Effective/Real 00 Effective (MSR[IS] = don’t care) 01 Reserved IAC1ER 10 Virtual (MSR[IS] = 0) 11 Virtual (MSR[IS] = 1) IAC 2 User/Supervisor 00 Both 01 Reserved IAC2US 10 Supervisor only (MSR[PR] = 0)
Page 242 User’s Manual PPC440x5 CPU Core Preliminary IAC3/4 Auto-Toggle Enable 0 Disable IAC 3/4 auto-toggle IAC34AT 1 Enable IAC 3/4 auto-toggle debug.fm. Page 242 of 589 September 12, 2002...
Page 243: Debug Control Register 2 (Dbcr2)
User’s Manual Preliminary PPC440x5 CPU Core 8.6.3 Debug Control Register 2 (DBCR2) DBCR2 is an SPR that is used to configure DAC and DVC debug events. DBCR2 can be written from a GPR using mtspr , and can be read into a GPR using mfspr .
Page 244: Debug Status Register (Dbsr)
User’s Manual PPC440x5 CPU Core Preliminary DVC 2 Mode 00 Reserved 01 AND all bytes enabled by DVC2BE 14:15 DVC2M 10 OR all bytes enabled by DVC2BE 11 AND-OR pairs of bytes enabled by DVC2BE (0 AND 1) OR (2 AND 3)
Page 245: Instruction Address Compare Registers (Iac1-Iac4)
User’s Manual Preliminary PPC440x5 CPU Core Interrupt Debug Event 0 Event didn’t occur IRPT 1 Event occurred Trap Debug Event 0 Event didn’t occur TRAP 1 Event occurred IAC 1 Debug Event IAC1 0 Event didn’t occur 1 Event occurred IAC 2 Debug Event 0 Event didn’t occur...
Page 246: Data Address Compare Registers (Dac1-Dac2)
User’s Manual PPC440x5 CPU Core Preliminary 29 30 31 Figure 8-5. Instruction Address Compare Registers (IAC1–IAC4) 0:29 Instruction Address Compare (IAC) word address 30:31 Reserved 8.6.6 Data Address Compare Registers (DAC1–DAC2) The two DAC registers specify the addresses upon which DAC (and/or DVC) debug events should occur.
Page 247: Debug Data Register (Dbdr)
User’s Manual Preliminary PPC440x5 CPU Core 8.6.8 Debug Data Register (DBDR) The DBDR can be used for communication between software running on the processor and debug tool hard- ware and software. The DBDR can be written from a GPR using mtspr , and can be read into a GPR using mfspr .
Page 248 User’s Manual PPC440x5 CPU Core Preliminary debug.fm. Page 248 of 589 September 12, 2002...
Page 249: Instruction Set
Preliminary PPC440x5 CPU Core User’s Manual 9. Instruction Set Descriptions of the PPC440x5 instructions follow. Each description contains the following elements: • Instruction names (mnemonic and full) • Instruction syntax • Instruction format diagram • Pseudocode description • Prose description •...
Page 250: Instruction Set Portability
However, all of the allocated instructions which are implemented within the PPC440x5 core are “standard” for IBM PowerPC 400 Series family of embedded controllers, and are not unique to the PPC440x5. The allocated instructions implemented within the PPC440x5 are divided into four sub-categories, and are shown in Table 9-2.
Page 251: Pseudocode
Preliminary PPC440x5 CPU Core User’s Manual These instruction fields contain values, such as opcodes, that cannot be altered. The instruction format diagrams specify the values of defined fields. • Variable These fields contain operands, such as general purpose register specifiers and immediate values, each of which may contain any one of a number of values.
Page 252 PPC440x5 CPU Core User’s Manual Preliminary Effective address; the 32-bit address, derived by applying indexing or indirect addressing rules to the speciﬁed operand, that speciﬁes an location in main storage. EXTS(x) The result of extending on the left with sign bits.
Page 253: Operator Precedence
Preliminary PPC440x5 CPU Core User’s Manual instruction(EA) An instruction operating on a data or instruction cache block associated with an EA. leave Leave innermost do loop or do loop speciﬁed in a leave statement. A decimal number The bit or bit value is replicated times.
Page 254: Alphabetical Instruction Listing
PPC440x5 CPU Core User’s Manual Preliminary Common examples of these kinds of register changes include the Condition Register (CR) and the Integer Exception Register (XER). For discussion of the CR, see Condition Register (CR) on page 67. For discussion of the XER, see Integer Exception Register (XER) on page 72.
Page 255: Add
Preliminary PPC440x5 CPU Core User’s Manual OE= 0, Rc= 0 RT, RA, RB add. OE= 0, Rc= 1 RT, RA, RB addo OE= 1, Rc= 0 RT, RA, RB addo. OE= 1, Rc= 1 RT, RA, RB 21 22 (RT) (RA) + (RB) The sum of the contents of register RA and the contents of register RB is placed into register RT.
Page 256: Addc
Add Carrying PPC440x5 CPU Core User’s Manual Preliminary addc Add Carrying addc RT, RA, RB OE= 0, Rc= 0 addc. RT, RA, RB OE= 0, Rc= 1 addco RT, RA, RB OE= 1, Rc= 0 addco. RT, RA, RB...
Page 257: Adde
Add Extended Preliminary PPC440x5 CPU Core User’s Manual adde Add Extended adde RT, RA, RB OE= 0, Rc= 0 adde. RT, RA, RB OE= 0, Rc= 1 addeo RT, RA, RB OE= 1, Rc= 0 addeo. RT, RA, RB...
Page 258: Addi
Add Immediate PPC440x5 CPU Core User’s Manual Preliminary addi Add Immediate addi RT, RA, IM (RT) (RA|0) + EXTS(IM) If the RA field is 0, the IM field, sign-extended to 32 bits, is placed into register RT. If the RA field is nonzero, the sum of the contents of register RA and the contents of the IM field, sign- extended to 32 bits, is placed into register RT.
Page 259: Addic
Add Immediate Carrying Preliminary PPC440x5 CPU Core User’s Manual addic Add Immediate Carrying addic RT, RA, IM (RT) (RA) + EXTS(IM) if (RA) + EXTS(IM) – 1 then > XER[CA] else XER[CA] The sum of the contents of register RA and the contents of the IM field, sign-extended to 32 bits, is placed into register RT.
Page 260: Addic
Add Immediate Carrying and Record PPC440x5 CPU Core User’s Manual Preliminary addic. Add Immediate Carrying and Record addic. RT, RA, IM (RT) (RA) + EXTS(IM) if (RA) + EXTS(IM) – 1 then > XER[CA] else XER[CA] The sum of the contents of register RA and the contents of the IM field, sign-extended to 32 bits, is placed into register RT.
Page 261: Addis
Add Immediate Shifted Preliminary PPC440x5 CPU Core User’s Manual addis Add Immediate Shifted addis RT, RA, IM (RT) (RA|0) + (IM If the RA field is 0, the IM field is concatenated on its right with sixteen 0-bits and placed into register RT.
Page 262: Addme
Add to Minus One Extended PPC440x5 CPU Core User’s Manual Preliminary addme Add to Minus One Extended addme RT, RA OE= 0, Rc= 0 addme. RT, RA OE= 0, Rc= 1 addmeo RT, RA OE=1, Rc= 0 addmeo. RT, RA...
Page 263: Addze
Add to Zero Extended Preliminary PPC440x5 CPU Core User’s Manual addze Add to Zero Extended addze RT, RA OE=0, Rc=0 addze. RT, RA OE=0, Rc=1 addzeo RT, RA OE=1, Rc=0 addzeo. RT, RA OE=1, Rc=1 21 22 (RT) (RA) + XER[CA] if (RA) + XER[CA] –...
Page 264: And
PPC440x5 CPU Core User’s Manual Preliminary RA, RS, RB Rc=0 and. RA, RS, RB Rc=1 (RA) (RS) (RB) The contents of register RS are ANDed with the contents of register RB; the result is placed into register RA. Registers Altered •...
Page 265: Andc
AND with Complement Preliminary PPC440x5 CPU Core User’s Manual andc AND with Complement andc RA,RS,RB Rc=0 andc. RA,RS,RB Rc=1 21 2 (RA) (RS) (RB) The contents of register RS are ANDed with the ones complement of the contents of register RB; the result is placed into register RA.
Page 266: Andi
AND Immediate PPC440x5 CPU Core User’s Manual Preliminary andi. AND Immediate andi. RA, RS, IM (RA) (RS) The IM field is extended to 32 bits by concatenating 16 0-bits on its left. The contents of register RS is ANDed with the extended IM field;...
Page 267: Andis
AND Immediate Shifted Preliminary PPC440x5 CPU Core User’s Manual andis. AND Immediate Shifted andis. RA, RS, IM (RA) (RS) The IM field is extended to 32 bits by concatenating 16 0-bits on its right. The contents of register RS are ANDed with the extended IM field;...
Page 268 Branch PPC440x5 CPU Core User’s Manual Preliminary Branch target AA=0, LK=0 target AA=1, LK=0 target AA=0, LK=1 target AA=1, LK=1 AA LK 30 31 If AA = 1 then target 6:29 EXTS(LI else (target – CIA) 6:29 CIA + EXTS(LI...
Page 269 Branch Conditional Preliminary PPC440x5 CPU Core User’s Manual Branch Conditional BO, BI, target AA=0, LK= 0 BO, BI, target AA =1, LK= 0 BO, BI, target AA= 0, LK=1 bcla BO, BI, target AA =1, LK=1 AA LK 30 31...
Page 270: Table 9-8. Extended Mnemonics For Bc, Bca, Bcl, Bcla
Branch Conditional PPC440x5 CPU Core User’s Manual Preliminary Table 9-8. Extended Mnemonics for bc, bca, bcl, bcla Other Registers Mnemonic Operands Function Altered Decrement CTR; branch if CTR Extended mnemonic for bdnz bc 16,0,target Extended mnemonic for bdnza bca 16,0,target...
Page 271 Branch Conditional Preliminary PPC440x5 CPU Core User’s Manual Table 9-8. Extended Mnemonics for bc, bca, bcl, bcla (continued) Other Registers Mnemonic Operands Function Altered Decrement CTR Branch if CTR = 0 AND CR = 0. cr_bit bdzf Extended mnemonic for...
Page 272 Branch Conditional PPC440x5 CPU Core User’s Manual Preliminary Table 9-8. Extended Mnemonics for bc, bca, bcl, bcla (continued) Other Registers Mnemonic Operands Function Altered Branch if greater than or equal. Use CR0 if cr_field is omitted. Extended mnemonic for bc 4,4 cr_ﬁeld+0,target...
Page 273 Branch Conditional Preliminary PPC440x5 CPU Core User’s Manual Table 9-8. Extended Mnemonics for bc, bca, bcl, bcla (continued) Other Registers Mnemonic Operands Function Altered Branch if not equal. Use CR0 if cr_field is omitted. Extended mnemonic for bc 4,4 cr_ﬁeld+2,target...
Page 274 Branch Conditional PPC440x5 CPU Core User’s Manual Preliminary Table 9-8. Extended Mnemonics for bc, bca, bcl, bcla (continued) Other Registers Mnemonic Operands Function Altered Branch if not unordered. Use CR0 if cr_field is omitted. Extended mnemonic for bc 4,4 cr_ﬁeld+3,target...
Page 275: Bcctr
Branch Conditional to Count Register Preliminary PPC440x5 CPU Core User’s Manual bcctr Branch Conditional to Count Register bcctr BO, BI LK = 0 bcctrl BO, BI LK =1 if (BO = BO )) then 0:29 else CIA + 4...
Page 276 Branch Conditional to Count Register PPC440x5 CPU Core User’s Manual Preliminary Table 9-9. Extended Mnemonics for bcctr, bcctrl (continued) Other Registers Mnemonic Operands Function Altered Branch, if equal, to address in CTR Use CR0 if cr_field is omitted. beqctr...
Page 277 Branch Conditional to Count Register Preliminary PPC440x5 CPU Core User’s Manual Table 9-9. Extended Mnemonics for bcctr, bcctrl (continued) Other Registers Mnemonic Operands Function Altered Branch, if not greater than, to address in CTR. Use CR0 if cr_field is omitted.
Page 278: Bclr
Branch Conditional to Link Register PPC440x5 CPU Core User’s Manual Preliminary bclr Branch Conditional to Link Register bclr BO, BI LK = 0 bclrl BO, BI LK =1 if BO = 0 then CTR – 1 if (BO ((CTR = 0) = BO...
Page 279: Table 9-10. Extended Mnemonics For Bclr, Bclrl
Branch Conditional to Link Register Preliminary PPC440x5 CPU Core User’s Manual Table 9-10. Extended Mnemonics for bclr, bclrl Other Registers Mnemonic Operands Function Altered Branch unconditionally to address in LR. Extended mnemonic for bclr 20,0 Extended mnemonic for blrl (LR) CIA + 4.
Page 280 Branch Conditional to Link Register PPC440x5 CPU Core User’s Manual Preliminary Table 9-10. Extended Mnemonics for bclr, bclrl (continued) Other Registers Mnemonic Operands Function Altered Branch if equal to address in LR. Use CR0 if cr_field is omitted. beqlr...
Page 281 Branch Conditional to Link Register Preliminary PPC440x5 CPU Core User’s Manual Table 9-10. Extended Mnemonics for bclr, bclrl (continued) Other Registers Mnemonic Operands Function Altered Branch, if not greater than, to address in LR. Use CR0 if cr_field is omitted.
Page 282: Cmp
Compare PPC440x5 CPU Core User’s Manual Preliminary Compare BF, 0, RA, RB if (RA) < (RB) then c if (RA) > (RB) then c if (RA) = (RB) then c XER[SO] CR[CRn] The contents of register RA are compared with the contents of register RB using a 32-bit signed compare.
Page 283: Cmpi
Compare Immediate Preliminary PPC440x5 CPU Core User’s Manual cmpi Compare Immediate cmpi BF, 0, RA, IM if (RA) < EXTS(IM) then c if (RA) > EXTS(IM) then c if (RA) = EXTS(IM) then c XER[SO] CR[CRn] The IM field is sign-extended to 32 bits. The contents of register RA are compared with the extended IM field, using a 32-bit signed compare.
Page 284: Cmpl
Compare Logical PPC440x5 CPU Core User’s Manual Preliminary cmpl Compare Logical cmpl BF, 0, RA, RB if (RA) (RB) then c < if (RA) (RB) then c > if (RA) (RB) then c XER[SO] CR[CRn] The contents of register RA are compared with the contents of register RB, using a 32-bit unsigned compare.
Page 285: Cmpli
Compare Logical Immediate Preliminary PPC440x5 CPU Core User’s Manual cmpli Compare Logical Immediate cmpli BF, 0, RA, IM if (RA) 0 || IM) then c < if (RA) 0 || IM) then c > if (RA) 0 || IM) then c...
Page 286: Cntlzw
Count Leading Zeros Word PPC440x5 CPU Core User’s Manual Preliminary cntlzw Count Leading Zeros Word cntlzw RA, RS Rc=0 cntlzw. RA, RS Rc=1 do while n < 32 if (RS) = 1 then leave n + 1 (RA) The consecutive leading 0 bits in register RS are counted; the count is placed into register RA.
Page 287: Crand
Condition Register AND Preliminary PPC440x5 CPU Core User’s Manual crand Condition Register AND crand BT, BA, BB The CR bit specified by the BA field is ANDed with the CR bit specified by the BB field; the result is placed into the CR bit specified by the BT field.
Page 288: Crandc
Condition Register AND with Complement PPC440x5 CPU Core User’s Manual Preliminary crandc Condition Register AND with Complement crandc BT, BA, BB The CR bit specified by the BA field is ANDed with the ones complement of the CR bit specified by the BB field;...
Page 289: Creqv
Condition Register Equivalent Preliminary PPC440x5 CPU Core User’s Manual creqv Condition Register Equivalent creqv BT, BA, BB The CR bit specified by the BA field is XORed with the CR bit specified by the BB field; the ones complement of the result is placed into the CR bit specified by the BT field.
Page 290: Crnand
Condition Register NAND PPC440x5 CPU Core User’s Manual Preliminary crnand Condition Register NAND crnand BT, BA, BB The CR bit specified by the BA field is ANDed with the CR bit specified by the BB field; the ones complement of the result is placed into the CR bit specified by the BT field.
Page 291: Crnor
Condition Register NOR Preliminary PPC440x5 CPU Core User’s Manual crnor Condition Register NOR crnor BT, BA, BB The CR bit specified by the BA field is ORed with the CR bit specified by the BB field; the ones complement of the result is placed into the CR bit specified by the BT field.
Page 292: Cror
Condition Register OR PPC440x5 CPU Core User’s Manual Preliminary cror Condition Register OR cror BT, BA, BB The CR bit specified by the BA field is ORed with the CR bit specified by the BB field; the result is placed into the CR bit specified by the BT field.
Page 293: Crorc
Condition Register OR with Complement Preliminary PPC440x5 CPU Core User’s Manual crorc Condition Register OR with Complement crorc BT, BA, BB The condition register (CR) bit specified by the BA field is ORed with the ones complement of the CR bit specified by the BB field;...
Page 294: Crxor
Condition Register XOR PPC440x5 CPU Core User’s Manual Preliminary crxor Condition Register XOR crxor BT, BA, BB The CR bit specified by the BA field is XORed with the CR bit specified by the BB field; the result is placed into the CR bit specified by the BT field.
Page 295: Dcba
Data Cache Block Allocate Preliminary PPC440x5 CPU Core User’s Manual dcba Data Cache Block Allocate dcba RA, RB dcba is treated as a no-op by the PPC440x5 core. instrset.fm. Page 295 of 589 September 12, 2002...
Page 296: Dcbf
Data Cache Block Flush PPC440x5 CPU Core User’s Manual Preliminary dcbf Data Cache Block Flush dcbf RA, RB (RA|0) + (RB) DCBF(EA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 297: Dcbi
Data Cache Block Invalidate Preliminary PPC440x5 CPU Core User’s Manual dcbi Data Cache Block Invalidate dcbi RA, RB (RA|0) + (RB) DCBI(EA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 298: Dcbst
Data Cache Block Store PPC440x5 CPU Core User’s Manual Preliminary dcbst Data Cache Block Store dcbst RA, RB (RA|0) + (RB) DCBST(EA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 299: Dcbt
Data Cache Block Touch Preliminary PPC440x5 CPU Core User’s Manual dcbt Data Cache Block Touch dcbt RA, RB (RA|0) + (RB) DCBT(EA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 300: Dcbtst
Data Cache Block Touch for Store PPC440x5 CPU Core User’s Manual Preliminary dcbtst Data Cache Block Touch for Store dcbtst RA, RB (RA|0) + (RB) DCBTST(EA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 301 Data Cache Block Touch for Store Preliminary PPC440x5 CPU Core User’s Manual This instruction is considered a “load” with respect to data address compare (DAC) Debug exceptions. See Debug Interrupt on page 195 for more information. instrset.fm. Page 301 of 589...
Page 302: Dcbz
Data Cache Block Set to Zero PPC440x5 CPU Core User’s Manual Preliminary dcbz Data Cache Block Set to Zero dcbz RA, RB 1014 (RA|0) + (RB) DCBZ(EA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 303 Data Cache Block Set to Zero Preliminary PPC440x5 CPU Core User’s Manual This instruction is considered a “store” with respect to data address compare (DAC) Debug exceptions. See Debug Interrupt on page 195 for more information. instrset.fm. Page 303 of 589...
Page 304: Dccci
Data Cache Congruence Class Invalidate PPC440x5 CPU Core User’s Manual Preliminary dccci Data Cache Congruence Class Invalidate dccci RA, RB DCCCI This instruction flash invalidates the entire data cache array. The RA and RB operands are not used; previous implementations used these operands to calculate an effective address (EA) which specified the particular block or blocks to be invalidated.
Page 305: Dcread
Data Cache Read Preliminary PPC440x5 CPU Core User’s Manual dcread Data Cache Read dcread RT, RA, RB (RA|0) + (RB) INDEX 17:26 WORD 27:29 (RT) (data cache data)[INDEX,WORD] DCDBTRH (data cache tag high)[INDEX] DCDBTRL (data cache tag low)[INDEX] An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 306 Data Cache Read PPC440x5 CPU Core User’s Manual Preliminary Registers Altered • RT • DCDBTRH • DCDBTRL Invalid Instruction Forms • Reserved ﬁelds Programming Note Execution of this instruction is privileged. The PPC440x5 core does not support the use of the dcread instruction when the data cache controller is still in the process of performing cache operations associated with previously executed instructions (such as line fills and line flushes).
Page 307: Divw
Divide Word Preliminary PPC440x5 CPU Core User’s Manual divw Divide Word divw RT, RA, RB OE=0, Rc=0 divw. RT, RA, RB OE=0, Rc=1 divwo RT, RA, RB OE=1, Rc=0 divwo. RT, RA, RB OE=1, Rc=1 21 22 (RT) (RA) (RB) The contents of register RA are divided by the contents of register RB.
Page 308: Divwu
Divide Word Unsigned PPC440x5 CPU Core User’s Manual Preliminary divwu Divide Word Unsigned divwu RT, RA, RB OE=0, Rc=0 divwu. RT, RA, RB OE=0, Rc=1 divwuo RT, RA, RB OE=1, Rc=0 divwuo. RT, RA, RB OE=1, Rc=1 21 22...
Page 309: Dlmzb
Determine Leftmost Zero Byte Preliminary PPC440x5 CPU Core User’s Manual dlmzb determine left most zero byte dlmzb RA, RS, RB Rc=0 dlmzb. RA, RS, RB Rc=1 (RS) || (RB) i, x, y do while (x < 8) (y = 0)
Page 310: Eqv
Equivalent PPC440x5 CPU Core User’s Manual Preliminary Equivalent RA, RS, RB Rc=0 eqv. RA, RS, RB Rc=1 (RA) ((RS) (RB)) The contents of register RS are XORed with the contents of register RB; the ones complement of the result is placed into register RA.
Page 311: Extsb
Extend Sign Byte Preliminary PPC440x5 CPU Core User’s Manual extsb Extend Sign Byte extsb RA, RS Rc=0 extsb. RA, RS Rc=1 (RA) EXTS(RS) 24:31 The least significant byte of register RS is sign-extended to 32 bits by replicating bit 24 of the register into bits 0 through 23 of the result.
Page 312: Extsh
Extend Sign Halfword PPC440x5 CPU Core User’s Manual Preliminary extsh Extend Sign Halfword extsh RA, RS Rc=0 extsh. RA, RS Rc=1 (RA) EXTS(RS) 16:31 The least significant halfword of register RS is sign-extended to 32 bits by replicating bit 16 of the register into bits 0 through 15 of the result.
Page 313: Icbi
Instruction Cache Block Invalidate Preliminary PPC440x5 CPU Core User’s Manual icbi Instruction Cache Block Invalidate icbi RA, RB (RA 0) + (RB) ICBI(EA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 314: Icbt
Instruction Cache Block Touch PPC440x5 CPU Core User’s Manual Preliminary icbt Instruction Cache Block Touch icbt RA, RB (RA|0) + (RB) ICBT(EA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 315 Instruction Cache Block Touch Preliminary PPC440x5 CPU Core User’s Manual This instruction is considered a “load” with respect to Data Storage exceptions. See Data Storage Interrupt on page 181 for more information. This instruction is considered a “load” with respect to data address compare (DAC) Debug exceptions. See Debug Interrupt on page 195 for more information.
Page 316: Iccci
Instruction Cache Congruence Class Invalidate PPC440x5 CPU Core User’s Manual Preliminary iccci Instruction Cache Congruence Class Invalidate iccci RA, RB ICCCI This instruction flash invalidates the entire instruction cache array. The RA and RB operands are not used; previous implementations used these operands to calculate an effective address (EA) which specified the particular block or blocks to be invalidated.
Page 317: Icread
Instruction Cache Read Preliminary PPC440x5 CPU Core User’s Manual icread Instruction Cache Read icread RA, RB (RA|0) + (RB) INDEX 17:26 WORD 27:29 ICDBDR (instruction cache data)[INDEX,WORD] ICDBTRH (instruction cache tag high)[INDEX] ICDBTRL (instruction cache tag low)[INDEX] An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 318 Instruction Cache Read PPC440x5 CPU Core User’s Manual Preliminary Registers Altered • ICDBDR • ICDBTRH • ICDBTRL Invalid Instruction Forms • Reserved ﬁelds Programming Note Execution of this instruction is privileged. The PPC440x5 does not automatically synchronize context between an icread instruction and the subse- quent mfspr instructions which read the results of the icread instruction into GPRs.
Page 319: Isel
Integer Select Preliminary PPC440x5 CPU Core User’s Manual isel Add Immediate isel RT, RA, RB, CRb if CR[CRb] = 1 then (RT) (RA|0) else (RT) (RB) If CR[CRb] = 0, register RT is written with the contents of register RB.
Page 320: Isync
Instruction Synchronize PPC440x5 CPU Core User’s Manual Preliminary isync Instruction Synchronize isync isync instruction is a context synchronizing instruction. isync provides an ordering function for the effects of all instructions executed by the processor. Executing isync insures that all instructions preceding the isync instruction execute before isync completes, except that storage accesses caused by those instructions need not have completed.
Page 321: Lbz
Load Byte and Zero Preliminary PPC440x5 CPU Core User’s Manual Load Byte and Zero RT, D(RA) (RA|0) + EXTS(D) (RT) 0 || MS(EA,1) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits.
Page 322: Lbzu
Load Byte and Zero with Update PPC440x5 CPU Core User’s Manual Preliminary lbzu Load Byte and Zero with Update lbzu RT, D(RA) (RA|0) + EXTS(D) (RA) (RT) 0 || MS(EA,1) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits.
Page 323: Lbzux
Load Byte and Zero with Update Indexed Preliminary PPC440x5 CPU Core User’s Manual lbzux Load Byte and Zero with Update Indexed lbzux RT, RA, RB (RA|0) + (RB) (RA) (RT) 0 || MS(EA,1) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 324: Lbzx
Load Byte and Zero Indexed PPC440x5 CPU Core User’s Manual Preliminary lbzx Load Byte and Zero Indexed lbzx RT,RA, RB (RA|0) + (RB) (RT) 0 || MS(EA,1) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 325: Lha
Load Halfword Algebraic Preliminary PPC440x5 CPU Core User’s Manual Load Halfword Algebraic RT, D(RA) (RA|0) + EXTS(D) (RT) EXTS(MS(EA,2)) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
Page 326: Lhau
Load Halfword Algebraic with Update PPC440x5 CPU Core User’s Manual Preliminary lhau Load Halfword Algebraic with Update lhau RT, D(RA) (RA|0) + EXTS(D) (RA) (RT) EXTS(MS(EA,2)) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits.
Page 327: Lhaux
Load Halfword Algebraic with Update Indexed Preliminary PPC440x5 CPU Core User’s Manual lhaux Load Halfword Algebraic with Update Indexed lhaux RT, RA, RB (RA|0) + (RB) (RA) (RT) EXTS(MS(EA,2)) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 328: Lhax
Load Halfword Algebraic Indexed PPC440x5 CPU Core User’s Manual Preliminary lhax Load Halfword Algebraic Indexed lhax RT, RA, RB (RA|0) + (RB) (RT) EXTS(MS(EA,2)) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 329: Lhbrx
Load Halfword Byte-Reverse Indexed Preliminary PPC440x5 CPU Core User’s Manual lhbrx Load Halfword Byte-Reverse Indexed lhbrx RT, RA, RB (RA|0) + (RB) (RT) 0 || BYTE_REVERSE(MS(EA,2)) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 330: Lhz
Load Halfword and Zero PPC440x5 CPU Core User’s Manual Preliminary Load Halfword and Zero RT, D(RA) (RA|0) + EXTS(D) (RT) 0 || MS(EA,2) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits.
Page 331: Lhzu
Load Halfword and Zero with Update Preliminary PPC440x5 CPU Core User’s Manual lhzu Load Halfword and Zero with Update lhzu RT, D(RA) (RA|0) + EXTS(D) (RA) (RT) 0 || MS(EA,2) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits.
Page 332: Lhzux
Load Halfword and Zero with Update Indexed PPC440x5 CPU Core User’s Manual Preliminary lhzux Load Halfword and Zero with Update Indexed lhzux RT, RA, RB (RA|0) + (RB) (RA) (RT) 0 || MS(EA,2) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 333: Lhzx
Load Halfword and Zero Indexed Preliminary PPC440x5 CPU Core User’s Manual lhzx Load Halfword and Zero Indexed lhzx RT, RA, RB (RA|0) + (RB) (RT) 0 || MS(EA,2) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 334: Lmw
Load Multiple Word PPC440x5 CPU Core User’s Manual Preliminary Load Multiple Word RT, D(RA) (RA|0) + EXTS(D) do while r GPR(r)) MS(EA,4) r + 1 EA + 4 An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field in the instruction to 32 bits.
Page 335: Lswi
Load String Word Immediate Preliminary PPC440x5 CPU Core User’s Manual lswi Load String Word Immediate lswi RT, RA, NB (RA|0) if NB = 0 then else ((RT + CEIL(CNT/4) – 1) % 32) FINAL RT – 1 do while n > 0...
Page 336 Load String Word Immediate PPC440x5 CPU Core User’s Manual Preliminary • RA is in the range of registers to be loaded • RA = RT = 0 Programming Note This instruction can be restarted, meaning that it could be interrupted after having already updated some of the target registers, and then re-executed from the beginning (after returning from the interrupt), in which case the registers which had already been loaded prior to the interrupt will be loaded a second time.
Page 337: Lswx
Load String Word Indexed Preliminary PPC440x5 CPU Core User’s Manual lswx Load String Word Indexed lswx RT, RA, RB (RA|0) + (RB) XER[TBC] ((RT + CEIL(CNT/4) – 1) % 32) FINAL RT – 1 do while n > 0...
Page 338 Load String Word Indexed PPC440x5 CPU Core User’s Manual Preliminary Programming Note This instruction can be restarted, meaning that it could be interrupted after having already updated some of the target registers, and then re-executed from the beginning (after returning from the interrupt), in which case the registers which had already been loaded prior to the interrupt will be loaded a second time.
Page 339: Lwarx
Load Word and Reserve Indexed Preliminary PPC440x5 CPU Core User’s Manual lwarx Load Word and Reserve Indexed lwarx RT, RA, RB (RA|0) + (RB) RESERVE (RT) MS(EA,4) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 340: Lwbrx
Load Word Byte-Reverse Indexed PPC440x5 CPU Core User’s Manual Preliminary lwbrx Load Word Byte-Reverse Indexed lwbrx RT, RA, RB (RA|0) + (RB) (RT) BYTE_REVERSE(MS(EA,4)) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 341: Lwz
Load Word and Zero Preliminary PPC440x5 CPU Core User’s Manual Load Word and Zero RT, D(RA) (RA|0) + EXTS(D) (RT) MS(EA,4) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
Page 342: Lwzu
Load Word and Zero with Update PPC440x5 CPU Core User’s Manual Preliminary lwzu Load Word and Zero with Update lwzu RT, D(RA) (RA|0) + EXTS(D) (RA) (RT) MS(EA,4) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits.
Page 343: Lwzux
Load Word and Zero with Update Indexed Preliminary PPC440x5 CPU Core User’s Manual lwzux Load Word and Zero with Update Indexed lwzux RT, RA, RB (RA|0) + (RB) (RA) (RT) MS(EA,4) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 344: Lwzx
Load Word and Zero Indexed PPC440x5 CPU Core User’s Manual Preliminary lwzx Load Word and Zero Indexed lwzx RT, RA, RB (RA|0) + (RB) (RT) MS(EA,4) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 345: Macchw
Multiply Accumulate Cross Halfword to Word Modulo Signed Preliminary PPC440x5 CPU Core User’s Manual macchw Multiply Accumulate Cross Halfword to Word Modulo Signed macchw RT, RA, RB OE=0, Rc=0 macchw. RT, RA, RB OE=0, Rc=1 macchwo RT, RA, RB OE=1, Rc=0 macchwo.
Page 346: Macchws
Multiply Accumulate Cross Halfword to Word Saturate Signed PPC440x5 CPU Core User’s Manual Preliminary macchws Multiply Accumulate Cross Halfword to Word Saturate Signed macchws RT, RA, RB OE=0, Rc=0 macchws. RT, RA, RB OE=0, Rc=1 macchwso RT, RA, RB OE=1, Rc=0 macchwso.
Page 347: Macchwsu
Multiply Accumulate Cross Halfword to Word Saturate Unsigned Preliminary PPC440x5 CPU Core User’s Manual macchwsu Multiply Accumulate Cross Halfword to Word Saturate Unsigned macchwsu RT, RA, RB OE=0, Rc=0 macchwsu. RT, RA, RB OE=0, Rc=1 macchwsuo RT, RA, RB OE=1, Rc=0 macchwsuo.
Page 348: Macchwu
Multiply Accumulate Cross Halfword to Word Modulo Unsigned PPC440x5 CPU Core User’s Manual Preliminary macchwu Multiply Accumulate Cross Halfword to Word Modulo Unsigned macchwu RT, RA, RB OE=0, Rc=0 macchwu. RT, RA, RB OE=0, Rc=1 macchwuo RT, RA, RB OE=1, Rc=0 macchwuo.
Page 349: Machhw
Multiply Accumulate High Halfword to Word Modulo Signed Preliminary PPC440x5 CPU Core User’s Manual machhw Multiply Accumulate High Halfword to Word Modulo Signed machhw RT, RA, RB OE=0, Rc=0 machhw. RT, RA, RB OE=0, Rc=1 machhwo RT, RA, RB OE=1, Rc=0 machhwo.
Page 350: Machhws
Multiply Accumulate High Halfword to Word Saturate Signed PPC440x5 CPU Core User’s Manual Preliminary machhws Multiply Accumulate High Halfword to Word Saturate Signed machhws RT, RA, RB OE=0, Rc=0 machhws. RT, RA, RB OE=0, Rc=1 machhwso RT, RA, RB OE=1, Rc=0 machhwso.
Page 351: Machhwsu
Multiply Accumulate High Halfword to Word Saturate Unsigned Preliminary PPC440x5 CPU Core User’s Manual machhwsu Multiply Accumulate High Halfword to Word Saturate Unsigned machhwsu RT, RA, RB OE=0, Rc=0 machhwsu. RT, RA, RB OE=0, Rc=1 machhwsuo RT, RA, RB OE=1, Rc=0 machhwsuo.
Page 352: Machhwu
Multiply Accumulate High Halfword to Word Modulo Unsigned PPC440x5 CPU Core User’s Manual Preliminary machhwu Multiply Accumulate High Halfword to Word Modulo Unsigned machhwu RT, RA, RB OE=0, Rc=0 machhwu. RT, RA, RB OE=0, Rc=1 machhwuo RT, RA, RB OE=1, Rc=0 machhwuo.
Page 353: Maclhw
Multiply Accumulate Low Halfword to Word Modulo Signed Preliminary PPC440x5 CPU Core User’s Manual maclhw Multiply Accumulate Low Halfword to Word Modulo Signed maclhw RT, RA, RB OE=0, Rc=0 maclhw. RT, RA, RB OE=0, Rc=1 maclhwo RT, RA, RB OE=1, Rc=0 maclhwo.
Page 354: Maclhws
Multiply Accumulate Low Halfword to Word Saturate Signed PPC440x5 CPU Core User’s Manual Preliminary maclhws Multiply Accumulate Low Halfword to Word Saturate Signed maclhws RT, RA, RB OE=0, Rc=0 maclhws. RT, RA, RB OE=0, Rc=1 maclhwso RT, RA, RB OE=1, Rc=0 maclhwso.
Page 355: Maclhwsu
Multiply Accumulate Low Halfword to Word Saturate Unsigned Preliminary PPC440x5 CPU Core User’s Manual maclhwsu Multiply Accumulate Low Halfword to Word Saturate Unsigned maclhwsu RT, RA, RB OE=0, Rc=0 maclhwsu. RT, RA, RB OE=0, Rc=1 maclhwsuo RT, RA, RB OE=1, Rc=0 maclhwsuo.
Page 356: Maclhwu
Multiply Accumulate Low Halfword to Word Modulo Unsigned PPC440x5 CPU Core User’s Manual Preliminary maclhwu Multiply Accumulate Low Halfword to Word Modulo Unsigned maclhwu RT, RA, RB OE=0, Rc=0 maclhwu. RT, RA, RB OE=0, Rc=1 maclhwuo RT, RA, RB OE=1, Rc=0 maclhwuo.
Page 357: Mbar
Memory Barrier Preliminary PPC440x5 CPU Core User’s Manual mbar Memory Barrier mbar mbar instruction ensures that all loads and stores preceding mbar complete with respect to main mbar access main storage. storage before any loads and stores following If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Page 358: Mcrf
Move Condition Register Field PPC440x5 CPU Core User’s Manual Preliminary mcrf Move Condition Register Field mcrf BF, BFA (CR[CRn]) (CR[CRm]) The contents of the CR field specified by the BFA field are placed into the CR field specified by the BF field.
Page 359: Mcrxr
Move to Condition Register from XER Preliminary PPC440x5 CPU Core User’s Manual mcrxr Move to Condition Register from XER mcrxr (CR[CRn]) The contents of XER are placed into the CR field specified by the BF field. XER are then set to 0.
Page 360: Mfcr
Move From Condition Register PPC440x5 CPU Core User’s Manual Preliminary mfcr Move From Condition Register mfcr (RT) (CR) The contents of the CR are placed into register RT. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Page 361: Mfdcr
Move from Device Control Register Preliminary PPC440x5 CPU Core User’s Manual mfdcr Move from Device Control Register mfdcr RT, DCRN DCRF DCRN DCRF DCRF (RT) (DCR(DCRN)) The contents of the DCR specified by the DCRF field are placed into register RT.
Page 362: Mfmsr
Move From Machine State Register PPC440x5 CPU Core User’s Manual Preliminary mfmsr Move From Machine State Register mfmsr (RT) (MSR) The contents of the MSR are placed into register RT. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Page 363: Mfspr
Move From Special Purpose Register Preliminary PPC440x5 CPU Core User’s Manual mfspr Move From Special Purpose Register mfspr RT, SPRN SPRF SPRN SPRF SPRF (RT) (SPR(SPRN)) The contents of the SPR specified by the SPRF field are placed into register RT. See Special Purpose Regis- ters Sorted by SPR Number on page 454 for a listing of SPR mnemonics and corresponding SPRN values.
Page 364: Table 9-19. Extended Mnemonics For Mfspr
Move From Special Purpose Register PPC440x5 CPU Core User’s Manual Preliminary Table 9-19. Extended Mnemonics for mfspr Mnemonic Operands Function mfccr0 mfccr1 mfcsrr0 mfcsrr1 mfctr mfdac1 mfdac2 mfdbcr0 mfdbcr1 mfdbcr2 mfdbdr mfdbsr mfdcdbtrh mfdcdbtrl mfdear mfdec mfdnv0 mfdnv1 mfdnv2...
Page 365 Move From Special Purpose Register Preliminary PPC440x5 CPU Core User’s Manual Table 9-19. Extended Mnemonics for mfspr (continued) Mnemonic Operands Function mﬁvor5 mﬁvor6 mﬁvor7 mﬁvor8 mﬁvor9 mﬁvor10 mﬁvor11 mﬁvor12 mﬁvor13 mﬁvor14 mﬁvor15 mﬁvpr mﬂr mfmcsr mfmcsrr0 mfmcsrr1 mfmmucr mfpid...
Page 366: Msync
Memory Synchronize PPC440x5 CPU Core User’s Manual Preliminary msync Memory Synchronize msync msync instruction guarantees that all instructions initiated by the processor preceding msync will msync completes, and that no subsequent instructions will be initiated by the processor complete before msync completes.
Page 367: Mtcrf
Move to Condition Register Fields Preliminary PPC440x5 CPU Core User’s Manual mtcrf Move to Condition Register Fields mtcrf FXM, RS 11 12 20 21 mask (FXM (FXM (FXM (FXM (CR) ((RS) mask) ((CR) mask) Some or all of the contents of register RS are placed into the CR as specified by the FXM field.
Page 368: Mtdcr
Move To Device Control Register PPC440x5 CPU Core User’s Manual Preliminary mtdcr Move To Device Control Register mtdcr DCRN, RS DCRF DCRN DCRF || DCRF (DCR(DCRN)) (RS) The contents of register RS are placed into the DCR specified by the DCRF field.
Page 369: Mtmsr
Move To Machine State Register Preliminary PPC440x5 CPU Core User’s Manual mtmsr Move To Machine State Register mtmsr (MSR) (RS) The contents of register RS are placed into the MSR. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Page 370: Mtspr
Move To Special Purpose Register PPC440x5 CPU Core User’s Manual Preliminary mtspr Move To Special Purpose Register mtspr SPRN, RS SPRF SPRN SPRF SPRF (SPR(SPRN)) (RS) The contents of register RS are placed into register RT. See Special Purpose Registers Sorted by SPR Number on page 454 for a listing of SPR mnemonics and corresponding SPRN values.
Page 371: Table 9-22. Extended Mnemonics For Mtspr
Move To Special Purpose Register Preliminary PPC440x5 CPU Core User’s Manual Table 9-22. Extended Mnemonics for mtspr Mnemonic Operands Function mtccr0 mtccr1 mtcsrr0 mtcsrr1 mtctr mtdac1 mtdac2 mtdbcr0 mtdbcr1 mtdbcr2 mtdbdr mtdbsr mtdear mtdec mtdecar mtdnv0 mtdnv1 mtdnv2 mtdnv3...
Page 372 Move To Special Purpose Register PPC440x5 CPU Core User’s Manual Preliminary Table 9-22. Extended Mnemonics for mtspr (continued) Mnemonic Operands Function mtivor5 mtivor6 mtivor7 mtivor8 mtivor9 mtivor10 mtivor11 mtivor12 mtivor13 mtivor14 mtivor15 mtivpr mtlr mtmcsr mtmcsrr0 mtmcsrr1 mtmmucr mtpid...
Page 373: Mulchw
Multiply Cross Halfword to Word Signed Preliminary PPC440x5 CPU Core User’s Manual mulchw Multiply Cross Halfword to Word Signed mulchw RT, RA, RB Rc=0 mulchw. RT, RA, RB Rc=1 (RT) (RA) (RB) signed 16:31 0:15 The low-order halfword of RA is multiplied by the high-order halfword of RB, considering both source oper- ands as signed integers.
Page 374: Mulchwu
Multiply Cross Halfword to Word Unsigned PPC440x5 CPU Core User’s Manual Preliminary mulchwu Multiply Cross Halfword to Word Unsigned mulchwu RT, RA, RB Rc=0 mulchwu. RT, RA, RB Rc=1 (RT) (RA) (RB) unsigned 16:31 0:15 The low-order halfword of RA is multiplied by the high-order halfword of RB, considering both source oper- ands as unsigned integers.
Page 375: Mulhhw
Multiply High Halfword to Word Signed Preliminary PPC440x5 CPU Core User’s Manual mulhhw Multiply High Halfword to Word Signed mulhhw RT, RA, RB Rc=0 mulhhw. RT, RA, RB Rc=1 (RT) (RA) (RB) signed 0:15 0:15 The high-order halfword of RA is multiplied by the high-order halfword of RB, considering both source oper- ands as signed integers.
Page 376: Mulhhwu
Multiply High Halfword to Word Unsigned PPC440x5 CPU Core User’s Manual Preliminary mulhhwu Multiply High Halfword to Word Unsigned mulhhwu RT, RA, RB Rc=0 mulhhwu. RT, RA, RB Rc=1 (RT) (RA) (RB) unsigned 0:15 0:15 The high-order halfword of RA is multiplied by the high-order halfword of RB, considering both source oper- ands as unsigned integers.
Page 377: Mulhw
Multiply High Word Preliminary PPC440x5 CPU Core User’s Manual mulhw Multiply High Word mulhw RT, RA, RB Rc=0 mulhw. RT, RA, RB Rc=1 21 22 prod (RA) (RB) signed 0:63 (RT) prod 0:31 The 64-bit signed product of registers RA and RB is formed. The most significant 32 bits of the result is placed into register RT.
Page 378: Mulhwu
Multiply High Word Unsigned PPC440x5 CPU Core User’s Manual Preliminary mulhwu Multiply High Word Unsigned mulhwu RT, RA, RB Rc=0 mulhwu. RT, RA, RB Rc=1 21 22 prod (RA) (RB) unsigned 0:63 (RT) prod 0:31 The 64-bit unsigned product of registers RA and RB is formed. The most significant 32 bits of the result are placed into register RT.
Page 379: Mullhw
Multiply Low Halfword to Word Signed Preliminary PPC440x5 CPU Core User’s Manual mullhw Multiply High Halfword to Word Signed mullhw RT, RA, RB Rc=0 mullhw. RT, RA, RB Rc=1 (RT) (RA) (RB) signed 16:31 16:31 The low-order halfword of RA is multiplied by the low-order halfword of RB, considering both source operands as signed integers.
Page 380: Mullhwu
Multiply Low Halfword to Word Unsigned PPC440x5 CPU Core User’s Manual Preliminary mullhwu Multiply High Halfword to Word Unsigned mullhwu RT, RA, RB Rc=0 mullhwu. RT, RA, RB Rc=1 (RT) (RA) (RB) unsigned 16:31 16:31 The low-order halfword of RA is multiplied by the low-order halfword of RB, considering both source operands as unsigned integers.
Page 381: Mulli
Multiply Low Immediate Preliminary PPC440x5 CPU Core User’s Manual mulli Multiply Low Immediate mulli RT, RA, IM prod (RA) 0:47 (RT) prod 16:47 The 48-bit product of register RA and the 16-bit IM field is formed. The least significant 32 bits of the product are placed into register RT.
Page 382: Mullw
Multiply Low Word PPC440x5 CPU Core User’s Manual Preliminary mullw Multiply Low Word mullw RT, RA, RB OE=0, Rc=0 mullw. RT, RA, RB OE=0, Rc=1 mullwo RT, RA, RB OE=1, Rc=0 mullwo. RT, RA, RB OE=1, Rc=1 21 22...
Page 383: Nand
NAND Preliminary PPC440x5 CPU Core User’s Manual nand NAND nand RA, RS, RB Rc=0 nand. RA, RS, RB Rc=1 (RA) ((RS) (RB)) The contents of register RS is ANDed with the contents of register RB; the ones complement of the result is placed into register RA.
Page 384: Neg
Negate PPC440x5 CPU Core User’s Manual Preliminary Negate RT, RA OE=0, Rc=0 neg. RT, RA OE=0, Rc=1 nego RT, RA OE=1, Rc=0 nego. RT, RA OE=1, Rc=1 21 22 (RT) (RA) + 1 The twos complement of the contents of register RA are placed into register RT.
Page 385: Nmacchw
Negative Multiply Accumulate Cross Halfword to Word Modulo Signed Preliminary PPC440x5 CPU Core User’s Manual nmacchw Negative Multiply Accumulate Cross Halfword to Word Modulo Signed nmacchw RT, RA, RB OE=0, Rc=0 nmacchw. RT, RA, RB OE=0, Rc=1 nmacchwo RT, RA, RB OE=1, Rc=0 nmacchwo.
Page 386: Nmacchws
Negative Multiply Accumulate Cross Halfword to Word Saturate Signed PPC440x5 CPU Core User’s Manual Preliminary nmacchws Negative Multiply Accumulate High Halfword to Word Saturate Signed nmacchws RT, RA, RB OE=0, Rc=0 nmacchws. RT, RA, RB OE=0, Rc=1 nmacchwso RT, RA, RB OE=1, Rc=0 nmacchwso.
Page 387: Nmachhw
Negative Multiply Accumulate High Halfword to Word Modulo Signed Preliminary PPC440x5 CPU Core User’s Manual nmachhw Negative Multiply Accumulate High Halfword to Word Modulo Signed nmachhw RT, RA, RB OE=0, Rc=0 nmachhw. RT, RA, RB OE=0, Rc=1 nmachhwo RT, RA, RB OE=1, Rc=0 nmachhwo.
Page 388: Nmachhws
Negative Multiply Accumulate High Halfword to Word Saturate Signed PPC440x5 CPU Core User’s Manual Preliminary nmachhws Negative Multiply Accumulate High Halfword to Word Saturate Signed nmachhws RT, RA, RB OE=0, Rc=0 nmachhws. RT, RA, RB OE=0, Rc=1 nmachhwso RT, RA, RB OE=1, Rc=0 nmachhwso.
Page 389: Nmaclhw
Negative Multiply Accumulate Low Halfword to Word Modulo Signed Preliminary PPC440x5 CPU Core User’s Manual nmaclhw Negative Multiply Accumulate Low Halfword to Word Modulo Signed nmaclhw RT, RA, RB OE=0, Rc=0 nmaclhw. RT, RA, RB OE=0, Rc=1 nmaclhwo RT, RA, RB OE=1, Rc=0 nmaclhwo.
Page 390: Nmaclhws
Negative Multiply Accumulate High Halfword to Word Saturate Signed PPC440x5 CPU Core User’s Manual Preliminary nmaclhws Negative Multiply Accumulate Low Halfword to Word Saturate Signed nmaclhws RT, RA, RB OE=0, Rc=0 nmaclhws. RT, RA, RB OE=0, Rc=1 nmaclhwso RT, RA, RB OE=1, Rc=0 nmaclhwso.
Page 391: Nor
Preliminary PPC440x5 CPU Core User’s Manual RA, RS, RB Rc=0 nor. RA, RS, RB Rc=1 (RA) ((RS) (RB)) The contents of register RS is ORed with the contents of register RB; the ones complement of the result is placed into register RA.
Page 392: Table 9-24. Extended Mnemonics For Or, Or
PPC440x5 CPU Core User’s Manual Preliminary RA, RS, RB Rc=0 RA, RS, RB Rc=1 (RA) (RS) (RB) The contents of register RS is ORed with the contents of register RB; the result is placed into register RA. Registers Altered • RA •...
Page 393: Orc
OR with Complement Preliminary PPC440x5 CPU Core User’s Manual OR with Complement RA, RS, RB Rc=0 orc. RA, RS, RB Rc=1 (RA) (RS) (RB) The contents of register RS is ORed with the ones complement of the contents of register RB; the result is placed into register RA.
Page 394: Ori
OR Immediate PPC440x5 CPU Core User’s Manual Preliminary OR Immediate RA, RS, IM (RA) (RS) 0 || IM) The IM field is extended to 32 bits by concatenating 16 0-bits on the left. Register RS is ORed with the extended IM field; the result is placed into register RA.
Page 395: Oris
OR Immediate Shifted Preliminary PPC440x5 CPU Core User’s Manual oris OR Immediate Shifted oris RA, RS, IM (RA) (RS) The IM Field is extended to 32 bits by concatenating 16 0-bits on the right. Register RS is ORed with the extended IM field and the result is placed into register RA.
Page 396: Rfci
Return From Critical Interrupt PPC440x5 CPU Core User’s Manual Preliminary rfci Return From Critical Interrupt rfci (PC) (CSRR0) (MSR (CSRR1) This instruction is used to return from a critical interrupt. The program counter (PC) is restored with the contents of CSRR0 and the MSR is restored with the contents of CSRR1.
Page 397: Rfi
Return From Interrupt Preliminary PPC440x5 CPU Core User’s Manual rﬁ Return From Interrupt rﬁ (PC) (SRR0) (MSR) (SRR1) This instruction is used to return from a non-critical interrupt. The program counter (PC) is restored with the contents of SRR0 and the MSR is restored with the contents of SRR1.
Page 398: Rfmci
Return From Machine Check Interrupt PPC440x5 CPU Core User’s Manual Preliminary rfmci Return From Critical Interrupt rfmci (PC) (MCSRR0) (MSR (MCSRR1) This instruction is used to return from a machine check interrupt. The program counter (PC) is restored with the contents of MCSRR0 and the MSR is restored with the contents of MCSRR1.
Page 399: Rlwimi
Rotate Left Word Immediate then Mask Insert Preliminary PPC440x5 CPU Core User’s Manual rlwimi Rotate Left Word Immediate then Mask Insert rlwimi RA, RS, SH, MB, ME Rc=0 rlwimi. RA, RS, SH, MB, ME Rc=1 ROTL((RS), SH) MASK(MB, ME)
Page 400: Rlwinm
Rotate Left Word Immediate then AND with Mask PPC440x5 CPU Core User’s Manual Preliminary rlwinm Rotate Left Word Immediate then AND with Mask rlwinm RA, RS, SH, MB, ME Rc=0 rlwinm. RA, RS, SH, MB, ME Rc=1 ROTL((RS), SH)
Page 401 Rotate Left Word Immediate then AND with Mask Preliminary PPC440x5 CPU Core User’s Manual Table 9-27. Extended Mnemonics for rlwinm, rlwinm. (continued) Other Registers Mnemonic Operands Function Altered Clear right immediate. ( < 32) (RA) 32-n:31 clrrwi Extended mnemonic for...
Page 402 Rotate Left Word Immediate then AND with Mask PPC440x5 CPU Core User’s Manual Preliminary Table 9-27. Extended Mnemonics for rlwinm, rlwinm. (continued) Other Registers Mnemonic Operands Function Altered Shift right immediate. ( < 32) (RA) n:31 (RS) 0:31-n srwi...
Page 403: Rlwnm
Rotate Left Word then AND with Mask Preliminary PPC440x5 CPU Core User’s Manual rlwnm Rotate Left Word then AND with Mask rlwnm RA, RS, RB, MB, ME Rc=0 rlwnm. RA, RS, RB, MB, ME Rc=1 ROTL((RS), (RB) 27:31 MASK(MB, ME)
Page 404 System Call PPC440x5 CPU Core User’s Manual Preliminary System Call 30 31 SRR1 SRR0 4 + address of sc instruction IVPR || IVOR8 0:15 16:27 MSR[WE, EE, PR, FP, FE0, FE1, DWE, DS, IS] A System Call exception is generated, and a System Call interrupt occurs (see System Call Interrupt on page 190 for more information on System Call interrupts).
Page 405: Slw
Shift Left Word Preliminary PPC440x5 CPU Core User’s Manual Shift Left Word RA, RS, RB Rc=0 slw. RA, RS, RB Rc=1 (RB) 26:31 ROTL((RS), n) if n < 32 then MASK(0, 31 – n) else (RA) The contents of register RS are shifted left by the number of bits specified by the contents of register RB 26:31 Bits shifted left out of the most significant bit are lost, and 0-bits fill vacated bit positions on the right.
Page 406: Sraw
Shift Right Algebraic Word PPC440x5 CPU Core User’s Manual Preliminary sraw Shift Right Algebraic Word sraw RA, RS, RB Rc=0 sraw. RA, RS, RB Rc=1 (RB) 26:31 ROTL((RS), 32 – n) if n < 32 then MASK(n, 31) else...
Page 407: Srawi
Shift Right Algebraic Word Immediate Preliminary PPC440x5 CPU Core User’s Manual srawi Shift Right Algebraic Word Immediate srawi RA, RS, SH Rc=0 srawi. RA, RS, SH Rc=1 ROTL((RS), 32 – n) MASK(n, 31) (RS) (RA) XER[CA] m) 0) The contents of register RS are shifted right by the number of bits specified in the SH field. Bits shifted out of the least significant bit are lost.
Page 408: Srw
Shift Right Word PPC440x5 CPU Core User’s Manual Preliminary Shift Right Word RA, RS, RB Rc=0 srw. RA, RS, RB Rc=1 (RB) 26:31 ROTL((RS), 32 – n) if n < 32 then MASK(n, 31) else (RA) The contents of register RS are shifted right by the number of bits specified the contents of register RB 26:31 Bits shifted right out of the least significant bit are lost, and 0-bits fill the vacated bit positions on the left.
Page 409: Stb
Store Byte Preliminary PPC440x5 CPU Core User’s Manual Store Byte RS, D(RA) (RA|0) + EXTS(D) MS(EA, 1) (RS) 24:31 An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits. The base address is 0 when the RA field is 0, and is the contents of register RA otherwise.
Page 410: Stbu
Store Byte with Update PPC440x5 CPU Core User’s Manual Preliminary stbu Store Byte with Update stbu RS, D(RA) (RA|0) + EXTS(D) MS(EA, 1) (RS) 24:31 (RA) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits.
Page 411: Stbux
Store Byte with Update Indexed Preliminary PPC440x5 CPU Core User’s Manual stbux Store Byte with Update Indexed stbux RS, RA, RB (RA|0) + (RB) MS(EA, 1) (RS) 24:31 (RA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 412: Stbx
Store Byte Indexed PPC440x5 CPU Core User’s Manual Preliminary stbx Store Byte Indexed stbx RS, RA, RB (RA|0) + (RB) MS(EA, 1) (RS) 24:31 An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 413: Sth
Store Halfword Preliminary PPC440x5 CPU Core User’s Manual Store Halfword RS, D(RA) (RA|0) + EXTS(D) MS(EA, 2) (RS) 16:31 An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits. The base address is 0 when the RA field is 0 and is the contents of register RA otherwise.
Page 414: Sthbrx
Store Halfword Byte-Reverse Indexed PPC440x5 CPU Core User’s Manual Preliminary sthbrx Store Halfword Byte-Reverse Indexed sthbrx RS, RA, RB (RA|0) + (RB) MS(EA, 2) BYTE_REVERSE((RS) 16:31 An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 415: Sthu
Store Halfword with Update Preliminary PPC440x5 CPU Core User’s Manual sthu Store Halfword with Update sthu RS, D(RA) (RA|0) + EXTS(D) MS(EA, 2) (RS) 16:31 (RA) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits.
Page 416: Sthux
Store Halfword with Update Indexed PPC440x5 CPU Core User’s Manual Preliminary sthux Store Halfword with Update Indexed sthux RS, RA, RB (RA|0) + (RB) MS(EA, 2) (RS) 16:31 (RA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 417: Sthx
Store Halfword Indexed Preliminary PPC440x5 CPU Core User’s Manual sthx Store Halfword Indexed sthx RS, RA, RB (RA|0) + (RB) MS(EA, 2) (RS) 16:31 An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 418: Stmw
Store Multiple Word PPC440x5 CPU Core User’s Manual Preliminary stmw Store Multiple Word stmw RS, D(RA) (RA|0) + EXTS(D) do while r MS(EA, 4) (GPR(r)) r + 1 EA + 4 An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits.
Page 419: Stswi
Store String Word Immediate Preliminary PPC440x5 CPU Core User’s Manual stswi Store String Word Immediate stswi RS, RA, NB (RA|0) if NB = 0 then else RS – 1 do while n > 0 if i = 0 then...
Page 420 Store String Word Immediate PPC440x5 CPU Core User’s Manual Preliminary Programming Note This instruction can be restarted, meaning that it could be interrupted after having already stored some of the register values to memory, and then re-executed from the beginning (after returning from the interrupt), in which case the registers which had already been stored prior to the interrupt will be stored a second time.
Page 421: Stswx
Store String Word Indexed Preliminary PPC440x5 CPU Core User’s Manual stswx Store String Word Indexed stswx RS, RA, RB (RA|0) + (RB) XER[TBC] RS – 1 do while n > 0 if i = 0 then r + 1...
Page 422: Stw
Store Word PPC440x5 CPU Core User’s Manual Preliminary Store Word RS, D(RA) (RA|0) + EXTS(D) MS(EA, 4) (RS) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits. The base address is 0 when the RA field is 0, and is the contents of register RA otherwise.
Page 423: Stwbrx
Store Word Byte-Reverse Indexed Preliminary PPC440x5 CPU Core User’s Manual stwbrx Store Word Byte-Reverse Indexed stwbrx RS, RA, RB (RA|0) + (RB) MS(EA, 4) BYTE_REVERSE((RS) 0:31 An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 424: Stwcx
Store Word Conditional Indexed PPC440x5 CPU Core User’s Manual Preliminary stwcx. Store Word Conditional Indexed stwcx. RS, RA, RB (RA|0) + (RB) if RESERVE = 1 then MS(EA, 4) (RS) RESERVE (CR[CR0]) XER[SO] else (CR[CR0]) XER[SO] An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 425 Store Word Conditional Indexed Preliminary PPC440x5 CPU Core User’s Manual The PowerPC Book-E architecture also specifies that it is implementation-dependent as to whether a Data Storage, Data TLB Error, Alignment, or Debug interrupt occurs when the reservation bit is off at the time of stwcx.
Page 426: Stwu
Store Word with Update PPC440x5 CPU Core User’s Manual Preliminary stwu Store Word with Update stwu RS, D(RA) (RA|0) + EXTS(D) MS(EA, 4) (RS) (RA) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits.
Page 427: Stwux
Store Word with Update Indexed Preliminary PPC440x5 CPU Core User’s Manual stwux Store Word with Update Indexed stwux RS, RA, RB (RA|0) + (RB) MS(EA, 4) (RS) (RA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 428: Stwx
Store Word Indexed PPC440x5 CPU Core User’s Manual Preliminary stwx Store Word Indexed stwx RS, RA, RB (RA|0) + (RB) MS(EA,4) (RS) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 429: Subf
Subtract From Preliminary PPC440x5 CPU Core User’s Manual subf Subtract From subf RT, RA, RB OE=0, Rc=0 subf. RT, RA, RB OE=0, Rc=1 subfo RT, RA, RB OE=1, Rc=0 subfo. RT, RA, RB OE=1, Rc=1 21 22 (RT) (RA) + (RB) + 1 The sum of the ones complement of register RA, register RB, and 1 is stored into register RT.
Page 430: Subfc
Subtract From Carrying PPC440x5 CPU Core User’s Manual Preliminary subfc Subtract From Carrying subfc RT, RA, RB OE=0, Rc=0 subfc. RT, RA, RB OE=0, Rc=1 subfco RT, RA, RB OE=1, Rc=0 subfco. RT, RA, RB OE=1, Rc=1 21 22...
Page 431: Subfe
Subtract From Extended Preliminary PPC440x5 CPU Core User’s Manual subfe Subtract From Extended subfe RT, RA, RB OE=0, Rc=0 subfe. RT, RA, RB OE=0, Rc=1 subfeo RT, RA, RB OE=1, Rc=0 subfeo. RT, RA, RB OE=1, Rc=1 21 22...
Page 432: Subfic
Subtract From Immediate Carrying PPC440x5 CPU Core User’s Manual Preliminary subﬁc Subtract From Immediate Carrying subﬁc RT, RA, IM (RT) (RA) + EXTS(IM) + 1 (RA) + EXTS(IM) + 1 – 1 then > XER[CA] else XER[CA] The sum of the ones complement of RA, the IM field sign-extended to 32 bits, and 1 is placed into register XER[CA] is set to a value determined by the unsigned magnitude of the result of the subtract operation.
Page 433: Subfme
Subtract from Minus One Extended Preliminary PPC440x5 CPU Core User’s Manual subfme Subtract from Minus One Extended subfme RT, RA OE=0, Rc=0 subfme. RT, RA OE=0, Rc=1 subfmeo RT, RA OE=1, Rc=0 subfmeo. RT, RA OE=1, Rc=1 21 22 (RT) (RA) –...
Page 434: Subfze
Subtract from Zero Extended PPC440x5 CPU Core User’s Manual Preliminary subfze Subtract from Zero Extended subfze RT, RA OE=0, Rc=0 subfze. RT, RA OE=0, Rc=1 subfzeo RT, RA OE=1, Rc=0 subfzeo. RT, RA OE=1, Rc=1 21 22 (RT) (RA) + XER[CA] (RA) + XER[CA] –...
Page 435: Tlbre
TLB Read Entry Preliminary PPC440x5 CPU Core User’s Manual tlbre TLB Read Entry tlbre RT, RA, WS tlbentry TLB[(RA) 26:31 if WS =0 (RT) tlbentry[EPN,V,TS,SIZE] 0:27 if CCR0[CRPE] = 0 (RT) 28:31 else (RT) TPAR 28:31 MMUCR[STID] tlbentry[TID] else if WS = 1...
Page 436 TLB Read Entry PPC440x5 CPU Core User’s Manual Preliminary Registers Altered • RT • MMUCR[STID] (if WS = 0) Invalid Instruction Forms • Reserved ﬁelds • Invalid WS value Programming Notes Execution of this instruction is privileged. The PPC440x5 core does not automatically synchronize the context of the MMUCR[STID] field between a tlbre instruction which updates the field, and a tlbsx[.] instruction which uses it as a source operand.
Page 437: Tlbsx
TLB Search Indexed Preliminary PPC440x5 CPU Core User’s Manual tlbsx TLB Search Indexed tlbsx RT, RA, RB Rc=0 tlbsx. RT, RA, RB Rc=1 (RA|0) + (RB) if Rc = 1 CR[CR0] CR[CR0] CR[CR0] XER[SO} if Valid TLB entry matching EA and MMUCR[STID,STS] is in the TLB then...
Page 438: Tlbsync
TLB Synchronize PPC440x5 CPU Core User’s Manual Preliminary tlbsync TLB Synchronize tlbsync The tlbsync instruction is provided by the PowerPC Book-E architecture to support synchronization of TLB operations between processors in a coherent multi-processor system. Since the PPC440x5 core does not support coherent multi-processing, this instruction performs no operation, and is provided only to facilitate code portability.
Page 439: Tlbwe
TLB Write Entry Preliminary PPC440x5 CPU Core User’s Manual tlbwe TLB Write Entry tlbwe RS, RA, WS tlbentry TLB[(RA) 26:31 if WS = 0 tlbentry[EPN,V,TS,SIZE] (RS) 0:27 tlbentry[TID] MMUCR[STID] else if WS = 1 tlbentry[RPN] (RS) 0:21 tlbentry[ERPN] (RS)
Page 440 Trap Word PPC440x5 CPU Core User’s Manual Preliminary Trap Word TO, RA, RB if ( ((RA) (RB) = 1) < ((RA) (RB) = 1) > ((RA) (RB) = 1) ((RA) (RB) = 1) < ((RA) (RB) = 1) ) >...
Page 441: Table 9-31. Extended Mnemonics For Tw
Trap Word Preliminary PPC440x5 CPU Core User’s Manual The enabling of trap debug events may affect the interrupt type caused by the execution of tw instruction. Specifically, trap instructions may be enabled to cause Debug interrupts instead of Program interrupts. See Trap (TRAP) Debug Event on page 234 for more details.
Page 442: Twng
Trap Word PPC440x5 CPU Core User’s Manual Preliminary Table 9-31. Extended Mnemonics for tw (continued) Other Registers Mnemonic Operands Function Altered Trap if (RA) not greater than (RB). Extended mnemonic for twng RA, RB tw 20,RA,RB Trap if (RA) not less than (RB).
Page 443: Twi
Trap Word Immediate Preliminary PPC440x5 CPU Core User’s Manual Trap Word Immediate TO, RA, IM if ( ((RA) EXTS(IM) = 1) < ((RA) EXTS(IM) = 1) > ((RA) EXTS(IM) = 1) ((RA) EXTS(IM) = 1) < ((RA) EXTS(IM) = 1) ) >...
Page 444: Table 9-32. Extended Mnemonics For Twi
Trap Word Immediate PPC440x5 CPU Core User’s Manual Preliminary The enabling of trap debug events may affect the interrupt type caused by the execution of tw instruction. Specifically, trap instructions may be enabled to cause Debug interrupts instead of Program interrupts. See Trap (TRAP) Debug Event on page 234 for more details.
Page 445: Twnli
Trap Word Immediate Preliminary PPC440x5 CPU Core User’s Manual Table 9-32. Extended Mnemonics for twi (continued) Other Registers Mnemonic Operands Function Altered Trap if (RA) not less than EXTS(IM). Extended mnemonic for twnli RA, IM twi 12,RA,IM instrset.fm. Page 445 of 589...
Page 446: Wrtee
Write External Enable PPC440x5 CPU Core User’s Manual Preliminary wrtee Write External Enable wrtee MSR[EE] (RS) MSR[EE] is set to the value specified by bit 16 of register RS. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Page 447: Wrteei
Write External Enable Immediate Preliminary PPC440x5 CPU Core User’s Manual wrteei Write External Enable Immediate wrteei 16 17 MSR[EE] MSR[EE] is set to the value specified by the E field. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Page 448: Xor
PPC440x5 CPU Core User’s Manual Preliminary RA, RS, RB Rc=0 xor. RA, RS, RB Rc=1 (RA) (RS) (RB) The contents of register RS are XORed with the contents of register RB; the result is placed into register RA. Registers Altered •...
Page 449: Xori
XOR Immediate Preliminary PPC440x5 CPU Core User’s Manual xori XOR Immediate xori RA, RS, IM (RA) (RS) 0 || IM) The IM field is extended to 32 bits by concatenating 16 0-bits on the left. The contents of register RS are XORed with the extended IM field;...
Page 450: Xoris
XOR Immediate Shifted PPC440x5 CPU Core User’s Manual Preliminary xoris XOR Immediate Shifted xoris RA, RS, IM (RA) (RS) (IM || The IM field is extended to 32 bits by concatenating 16 0-bits on the right. The contents of register RS are XORed with the extended IM field;...
Page 451: Register Summary
User’s Manual Preliminary PPC440x5 CPU Core 10. Register Summary This chapter provides an alphabetical listing of and bit definitions for the registers contained in the PPC440x5 core. The registers, of five types, are grouped into several functional categories according to the processor func- tions with which they are associated.
Page 452: Table 10-1. Register Categories
User’s Manual PPC440x5 CPU Core Preliminary Table 10-1. Register Categories Register Category Register(s) Model and Access Type Page User User Branch Control User DNV0–DNV3 Supervisor DTV0–DTV3 Supervisor DVLIM Supervisor Cache Control INV0–INV3 Supervisor ITV0–ITV3 Supervisor IVLIM Supervisor DCDBTRH, DCDBTRL Supervisor, read-only...
Page 453 User’s Manual Preliminary PPC440x5 CPU Core Table 10-1. Register Categories Register Category Register(s) Model and Access Type Page Supervisor DECAR Supervisor, write-only TBL, TBU User read, Supervisor write Timer Supervisor Supervisor regsummIntro.fm. September 12, 2002 Page 453 of 589...
Page 454: Table 10-2. Special Purpose Registers Sorted By Spr Number
User’s Manual PPC440x5 CPU Core Preliminary Table 10-2 Special Purpose Registers Sorted by SPR Number on page 454, lists the Special Purpose Regis- ters (SPRs) in order by SPR number (SPRN). The table provides mnemonics, names, SPRN, model (user or supervisor), and access.
Page 455 User’s Manual Preliminary PPC440x5 CPU Core Table 10-2. Special Purpose Registers Sorted by SPR Number Mnemonic Register Name SPRN Model Access SPRG3 Special Purpose Register General 3 0x113 Supervisor Read/Write SPRG4 Special Purpose Register General 4 0x114 Supervisor Write-only SPRG5...
Page 456 User’s Manual PPC440x5 CPU Core Preliminary Table 10-2. Special Purpose Registers Sorted by SPR Number Mnemonic Register Name SPRN Model Access IVOR14 Interrupt Vector Offset Register 14 0x19E Supervisor Read/Write IVOR15 Interrupt Vector Offset Register 15 0x19F Supervisor Read/Write MCSRR0...
Page 457: Reserved Fields
User’s Manual Preliminary PPC440x5 CPU Core 10.2 Reserved Fields For all registers with fields marked as reserved, the reserved fields should be written as zero and read as undefined. That is, when writing to a reserved field, write a zero to that field. When reading from a reserved field, ignore that field.
Page 458 User’s Manual PPC440x5 CPU Core Preliminary regsummIntro.fm. Page 458 of 589 September 12, 2002...
Page 459: Alphabetical Register Listing
Preliminary PPC440x5 CPU Core User’s Manual 0.Register Summary 10.4 Alphabetical Register Listing The following pages list the registers available in the PPC440x5 core. For each register, the following infor- mation is supplied: • Register mnemonic and name • Cross reference to detailed register information •...
Page 460: Ccr0
CCR0 Core Configuration Register 0 PPC440x5 CPU Core User’s Manual Preliminary CCR0 SPR 0x3B3 Supervisor R/W See Core Conﬁguration Register 0 (CCR0) on page 108. DSTG DTB GDCBT ICSLC 9 10 11 12 15 16 17 18 19 22 23 24...
Page 461 CCR0 (cont.) Core Configuration Register 0 Preliminary PPC440x5 CPU Core User’s Manual Force Load/Store Alignment 0 No Alignment exception on integer storage access instructions, regardless of alignment FLSTA See Load and Store Alignment on page 117. 1 An alignment exception occurs on integer storage access instructions if data address is not on an operand boundary.
Page 462: Ccr1
CCR1 Core Configuration Register 1 PPC440x5 CPU Core User’s Manual Preliminary CCR1 SPR 0x378 Supervisor R/W See Core Conﬁguration Register 1 (CCR1) on page 110. ICDPEI DCTPEI DCUPEI FCOM 9 10 11 12 13 14 15 16 19 20 21...
Page 463 CCR1 (cont.) Core Configuration Register 1 Preliminary PPC440x5 CPU Core User’s Manual Timer Clock Select 0 CPU timer advances by one at each rising edge of the CPU input clock (CPMC440CLOCK). When TCS = 1, CPU timer clock input can toggle 1 CPU timer advances by one for each rising edge at up to half of the CPU clock frequency.
Page 464: Figure 10-3. Condition Register (Cr)
Condition Register PPC440x5 CPU Core User’s Manual Preliminary User Read/Write See Condition Register (CR) on page 67. 11 12 15 16 19 20 23 24 27 28 Figure 10-3. Condition Register (CR) Condition Register Field 0 Condition Register Field 1...
Page 465: Csrr0
CSRR0 Critical Save/Restore Register 0 Preliminary PPC440x5 CPU Core User’s Manual CSRR0 SPR 0x03A Supervisor R/W See Critical Save/Restore Register 0 (CSRR0) on page 168. 29 30 31 Figure 10-4. Critical Save/Restore Register 0 (CSRR0) 0:29 Return address for critical interrupts...
Page 466: Csrr1
CSRR1 Critical Save/Restore Register 1 PPC440x5 CPU Core User’s Manual Preliminary CSRR1 SPR 0x03B Supervisor R/W See Critical Save/Restore Register 1 (CSRR1) on page 168. 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Figure 10-5.
Page 467: Ctr
Count Register Preliminary PPC440x5 CPU Core User’s Manual SPR 0x009 User R/W See Count Register (CTR) on page 67. Figure 10-6. Count Register (CTR) Used as count for branch conditional with decre- bcctr 0:31 Count ment instructions, or as target address for instructions regsumm440core.fm.
Page 468: Dac1-Dac2
DAC1–DAC2 Data Address Compare Registers PPC440x5 CPU Core User’s Manual Preliminary DAC1–DAC2 SPR 0x13C–0x13D Supervisor R/W See Data Address Compare Registers (DAC1–DAC2) on page 246. Figure 10-7. Data Address Compare Registers (DAC1–DAC2) 0:31 Data Address Compare (DAC) byte address regsumm440core.fm.
Page 469: Dbcr0
DBCR0 Debug Control Register 0 Preliminary PPC440x5 CPU Core User’s Manual DBCR0 SPR 0x134 Supervisor R/W See Debug Control Register 0 (DBCR0) on page 239. TRAP IAC2 IAC4 DAC1W DAC2W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17...
Page 470 DBCR0 (cont.) Debug Control Register 0 PPC440x5 CPU Core User’s Manual Preliminary Data Address Compare (DAC) 1 Read Debug Event 0 Disable DAC 1 read debug event. DAC1R 1 Enable DAC 1 read debug event. DAC 1 Write Debug Event 0 Disable DAC 1 write debug event.
Page 471: Dbcr1
DBCR1 Debug Control Register 1 Preliminary PPC440x5 CPU Core User’s Manual DBCR1 SPR 0x135 Supervisor R/W See Debug Control Register 1 (DBCR1) on page 240. IAC4US IAC1US IAC2US IAC12M IAC3US IAC34M 0 1 2 3 4 5 6 7 8 9 10...
Page 472 DBCR1 (cont.) Debug Control Register 1 PPC440x5 CPU Core User’s Manual Preliminary IAC 4 User/Supervisor 00 Both 01 Reserved 20:21 IAC4US 10 Supervisor only (MSR[PR] = 0) 11 User only (MSR[PR] = 1) IAC 4 Effective/Real 00 Effective (MSR[IS] = don’t care)
Page 473: Dbcr2
DBCR2 Debug Control Register 2 Preliminary PPC440x5 CPU Core User’s Manual DBCR2 SPR 0x136 Supervisor R/W See Debug Control Register 2 (DBCR2) on page 243. DAC2US DAC12M DVC1BE DAC1US DVC1M 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16...
Page 474 DBCR2 (cont.) Debug Control Register 2 PPC440x5 CPU Core User’s Manual Preliminary DVC 2 Mode 00 Reserved 01 AND all bytes enabled by DVC2BE 14:15 DVC2M 10 OR all bytes enabled by DVC2BE 11 AND-OR pairs of bytes enabled by DVC2BE...
Page 475: Dbdr
DBDR Debug Data Register Preliminary PPC440x5 CPU Core User’s Manual DBDR SPR 0x3F3 Supervisor R/W See Debug Data Register (DBDR) on page 247. Figure 10-11. Debug Data Register (DBDR) 0:31 Debug Data regsumm440core.fm. Page 475 of 589 September 12, 2002...
Page 476: Dbsr
DBSR Debug Status Register PPC440x5 CPU Core User’s Manual Preliminary DBSR SPR 0x130 Supervisor Read/Clear See Debug Status Register (DBSR) on page 244. TRAP IAC2 IAC4 DAC1W DAC2W IAC34ATS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17...
Page 477 DBSR (cont.) Debug Status Register Preliminary PPC440x5 CPU Core User’s Manual DAC 1 Write Debug Event 0 Event didn’t occur DAC1W 1 Event occurred DAC 2 Read Debug Event 0 Event didn’t occur DAC2R 1 Event occurred DAC 2 Write Debug Event DAC2W 0 Event didn’t occur...
Page 478: Dcdbtrh
DCDBTRH Data Cache Debug Tag Register High PPC440x5 CPU Core User’s Manual Preliminary DCDBTRH SPR 0x39D Supervisor Read-Only See dcread Operation on page 127. TERA 23 24 25 27 28 Figure 10-13. Data Cache Debug Tag Register High (DCDBTRH) Bits 0:23 of the lower 32 bits of the 36-bit real...
Page 479: Dcdbtrl
DCDBTRL Data Cache Debug Tag Register Low Preliminary PPC440x5 CPU Core User’s Manual DCDBTRL SPR 0x39C Supervisor Read-Only See dcread Operation on page 127. DPAR UPAR 12 13 14 15 16 19 20 23 24 27 28 29 30 31...
Page 480: Dear
DEAR Data Exception Address Register PPC440x5 CPU Core User’s Manual Preliminary DEAR SPR 0x03D Supervisor R/W See Data Exception Address Register (DEAR) on page 170. Figure 10-15. Data Exception Address Register (DEAR) Address of data exception for Data Storage, Align-...
Page 481: Dec
Decrementer Preliminary PPC440x5 CPU Core User’s Manual SPR 0x016 Supervisor R/W See Decrementer (DEC) on page 211. Figure 10-16. Decrementer (DEC) 0:31 Decrement value regsumm440core.fm. Page 481 of 589 September 12, 2002...
Page 482: Decar
DECAR Decrementer Auto-Reload PPC440x5 CPU Core User’s Manual Preliminary DECAR SPR 0x036 Supervisor Write-Only See Decrementer (DEC) on page 211. Figure 10-17. Decrementer Auto-Reload (DECAR) Copied to DEC at next time base clock when 0:31 Decrementer auto-reload value DEC = 1 and auto-reload is enabled (TCR[ARE] = 1).
Page 483: Dnv0-Dnv3
DNV0–DNV3 Data Cache Normal Victim 0–3 Preliminary PPC440x5 CPU Core User’s Manual DNV0–DNV3 SPR 0x390–0x393 Supervisor R/W See Cache Line Replacement Policy on page 96. VNDXA VNDXC 15 16 23 24 VNDXB VNDXD Figure 10-18. Data Cache Normal Victim Registers (DNV0–DNV3)
Page 484: Dtv0-Dtv3
DTV0–DTV3 Data Cache Transient Victim 0–3 PPC440x5 CPU Core User’s Manual Preliminary DTV0–DTV3 SPR 0x394–0x397 Supervisor R/W See Cache Line Replacement Policy on page 96. VNDXA VNDXC 15 16 23 24 VNDXB VNDXD Figure 10-19. Data Cache Transient Victim Registers (DTV0–DTV3)
Page 485: Dvc1-Dvc2
DVC1–DVC2 Data Value Compare Registers Preliminary PPC440x5 CPU Core User’s Manual DVC1–DVC2 SPR 0x13E–0x13F Supervisor R/W See Data Value Compare Registers (DVC1–DVC2) on page 246. Figure 10-20. Data Value Compare Registers (DVC1–DVC2) 0:31 Data value to compare regsumm440core.fm. Page 485 of 589...
Page 486: Dvlim
DVLIM Data Cache Victim Limit PPC440x5 CPU Core User’s Manual Preliminary DVLIM SPR 0x398 Supervisor R/W See Cache Locking and Transient Mechanism on page 99. TFLOOR NFLOOR 0 1 2 9 10 12 13 20 21 23 24 TCEILING Figure 10-21. Data Cache Victim Limit (DVLIM)
Page 487: Esr
Exception Syndrome Register Preliminary PPC440x5 CPU Core User’s Manual SPR 0x03E Supervisor R/W See Exception Syndrome Register (ESR) on page 172. PCRE PCRF 9 10 11 12 13 14 15 16 26 27 28 29 PCMP Figure 10-22. Exception Syndrome Register (ESR) Machine Check—Instruction Fetch Exception...
Page 488 ESR (cont.) Exception Syndrome Register PPC440x5 CPU Core User’s Manual Preliminary Byte Ordering Exception 0 Byte Ordering exception did not occur. 1 Byte Ordering exception occurred. Program Interrupt—Imprecise Exception This field is only set for a Floating-Point Enabled 0 Exception occurred precisely; SRR0 contains...
Page 489: Gpr0-Gpr31
General Purpose Registers Preliminary PPC440x5 CPU Core User’s Manual GPR0–GPR31 User R/W See General Purpose Registers (GPRs) on page 71. Figure 10-23. General Purpose Registers (R0-R31) 0:31 General Purpose Register data regsumm440core.fm. Page 489 of 589 September 12, 2002...
Page 490: Iac1-Iac4
IAC1–IAC4 Instruction Address Compare Registers PPC440x5 CPU Core User’s Manual Preliminary IAC1–IAC4 SPR 0x138–0x13B Supervisor R/W See Instruction Address Compare Registers (IAC1–IAC4) on page 245. 29 30 31 Figure 10-24. Instruction Address Compare Registers (IAC1–IAC4) 0:29 Instruction Address Compare (IAC) word address...
Page 491: Icdbdr
ICDBDR Instruction Cache Debug Data Register Preliminary PPC440x5 CPU Core User’s Manual ICDBDR SPR 0x3D3 Supervisor Read-Only See icread Operation on page 112. Figure 10-25. Instruction Cache Debug Data Register (ICDBDR) 0:31 Instruction machine code from instruction cache regsumm440core.fm. Page 491 of 589...
Page 492: Icdbtrh
ICDBTRH Instruction Cache Debug Tag Register High PPC440x5 CPU Core User’s Manual Preliminary ICDBTRH SPR 0x39F Supervisor Read-Only See icread Operation on page 112. TPAR 23 24 25 26 27 28 DAPAR Figure 10-26. Instruction Cache Debug Tag Register High (ICDBTRH)
Page 493: Icdbtrl
ICDBTRL Instruction Cache Debug Tag Register Low Preliminary PPC440x5 CPU Core User’s Manual ICDBTRL SPR 0x39E Supervisor Read-Only See icread Operation on page 112. 21 22 23 24 Figure 10-27. Instruction Cache Debug Tag Register Low (ICDBTRL) 0:21 Reserved The address space portion of the virtual address Translation Space associated with the cache line read by icread.
Page 494: Inv0-Inv3
INV0–INV3 Instruction Cache Normal Victim 0–3 PPC440x5 CPU Core User’s Manual Preliminary INV0–INV3 SPR 0x370–0x373 Supervisor R/W See Cache Line Replacement Policy on page 96. VNDXA VNDXC 15 16 23 24 VNDXB VNDXD Figure 10-28. Instruction Cache Normal Victim Registers (INV0–INV3)
Page 495: Itv0-Itv3
ITV0–ITV3 Instruction Cache Transient Victim 0–3 Preliminary PPC440x5 CPU Core User’s Manual ITV0–ITV3 SPR 0x374–0x377 Supervisor R/W See Cache Line Replacement Policy on page 96. VNDXA VNDXC 15 16 23 24 VNDXB VNDXD Figure 10-29. Instruction Cache Transient Victim Registers (ITV0–ITV3)
Page 496: Ivlim
IVLIM Instruction Cache Victim Limit PPC440x5 CPU Core User’s Manual Preliminary IVLIM SPR 0x399 Supervisor R/W See Cache Locking and Transient Mechanism on page 99. TFLOOR NFLOOR 0 1 2 9 10 12 13 20 21 23 24 TCEILING Figure 10-30. Instruction Cache Victim Limit (IVLIM)
Page 497: Ivor0-Ivor15
IVOR0–IVOR15 Interrupt Vector Offset Registers Preliminary PPC440x5 CPU Core User’s Manual IVOR0–IVOR15 SPR 0x190–0x19F Supervisor R/W See Interrupt Vector Offset Registers (IVOR0–IVOR15) on page 170. 15 16 27 28 Figure 10-31. Interrupt Vector Offset Registers (IVOR0–IVOR15) 0:15 Reserved 16:27 Interrupt Vector Offset...
Page 498: Ivpr
IVPR Interrupt Vector Prefix Register PPC440x5 CPU Core User’s Manual Preliminary IVPR SPR 0x03F Supervisor R/W See Interrupt Vector Preﬁx Register (IVPR) on page 171. 15 16 Figure 10-32. Interrupt Vector Preﬁx Register (IVPR) 0:15 Interrupt Vector Prefix 16:31 Reserved regsumm440core.fm.
Page 499: Figure 10-33. Link Register (Lr)
Link Register Preliminary PPC440x5 CPU Core User’s Manual SPR 0x008 User R/W See Link Register (LR) on page 66. Figure 10-33. Link Register (LR) bclr 0:31 Link Register contents Target address of instruction regsumm440core.fm. Page 499 of 589 September 12, 2002...
Page 500: Mcsr
MCSR Machine Check Status Register PPC440x5 CPU Core User’s Manual Preliminary MCSR SPR 0x23C Supervisor Read/Clear See Machine Check Status Register (MCSR) on page 174. TLBP IMPE DCSP 1 2 3 4 DCFP Figure 10-34. Machine Check Status Register (MCSR) Set when a machine check exception occurs that is handled in the asynchronous fashion.
Page 501: Mcsrr0
MCSRR0 Machine Check Save/Restore Register 0 Preliminary PPC440x5 CPU Core User’s Manual MCSRR0 SPR 0x23A Supervisor R/W See Machine Check Save/Restore Register 0 (MCSRR0) on page 169. 29 30 31 Figure 10-35. Machine Check Save/Restore Register 0 (MCSRR0) 0:29 Return address for machine check interrupts...
Page 502: Mcsrr1
MCSRR1 Machine Check Save/Restore Register 1 PPC440x5 CPU Core User’s Manual Preliminary MCSRR1 SPR 0x23B Supervisor R/W See Machine Check Save/Restore Register 1 (MCSRR1) on page 169. 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Figure 0-2.
Page 503: Mmucr
MMUCR Memory Management Control Register Preliminary PPC440x5 CPU Core User’s Manual MMUCR SPR 0x3B2 Supervisor R/W See Memory Management Unit Control Register (MMUCR) on page 148. STID SWOA U2SWOAE IULXE 6 7 8 9 10 11 12 13 14 15 16...
Page 504: Msr
Machine State Register PPC440x5 CPU Core User’s Manual Preliminary Supervisor R/W See Machine State Register (MSR) on page 165. 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Figure 10-37. Machine State Register (MSR)
Page 505 MSR (cont.) Machine State Register Preliminary PPC440x5 CPU Core User’s Manual Floating-point exception mode 1 0 If MSR[FE0] = 0, ignore exceptions mode; if MSR[FE0] = 1, imprecise recoverable mode 1 If MSR[FE0] = 0, imprecise non-recoverable mode; if MSR[FE0] = 1, precise mode...
Page 506: Pid
Process ID PPC440x5 CPU Core User’s Manual Preliminary SPR 0x030 Supervisor R/W See Process ID (PID) on page 151. 23 24 Figure 10-38. Process ID (PID) 0:23 Reserved 24:31 Process ID regsumm440core.fm. Page 506 of 589 September 12, 2002...
Page 507: Pir
Processor Identification Register Preliminary PPC440x5 CPU Core User’s Manual SPR 0x11E Supervisor Read-Only See Processor Identiﬁcation Register (PIR) on page 76. 27 28 Figure 10-39. Processor Identiﬁcation Register (PIR) 0:27 Reserved 28:31 Processor Identification Number (PIN) regsumm440core.fm. Page 507 of 589...
Page 508: Pvr
Processor Version Register PPC440x5 CPU Core User’s Manual Preliminary SPR 0x11F Supervisor Read-Only See Processor Version Register (PVR) on page 75. 11 12 Figure 10-40. Processor Version Register (PVR) 0:11 Owner Identifier Identifies the owner of a core. Implementation-specific value identifying the spe-...
Page 509: Rstcfg
RSTCFG Reset Configuration Preliminary PPC440x5 CPU Core User’s Manual RSTCFG SPR 39B Supervisor Read-Only See Reset Conﬁguration (RSTCFG) on page 79. 15 16 17 18 19 20 23 24 25 27 28 ERPN Figure 10-41. Reset Conﬁguration 0:15 Reserved U0 Storage Attribute 0 U0 storage attribute is disabled See Table 5-1 on page 135.
Page 510: Sprg0-Sprg7
SPRG0–SPRG7 Special Purpose Register General PPC440x5 CPU Core User’s Manual Preliminary SPRG0–SPRG7 SPR 0x104–0x107 (User/Supervisor Read-Only); SPR 0x110–0x113 (Supervisor R/W); SPR 0x114–0x117 (Supervisor Write-Only) See Special Purpose Registers General (USPRG0, SPRG0–SPRG7) on page 75. Figure 10-42. Special Purpose Registers General (SPRG0–SPRG7)
Page 511: Srr0
SRR0 Save/Restore Register 0 Preliminary PPC440x5 CPU Core User’s Manual SRR0 SPR 0x01A Supervisor R/W See Save/Restore Register 0 (SRR0) on page 167. 29 30 31 Figure 10-43. Save/Restore Register 0 (SRR0) 0:29 Return address for non-critical interrupts 30:31 Reserved regsumm440core.fm.
Page 512: Srr1
SRR1 Save/Restore Register 1 PPC440x5 CPU Core User’s Manual Preliminary SRR1 SPR 0x01B Supervisor R/W See Save/Restore Register 1 (SRR1) on page 167. 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Figure 10-44.
Page 513: Tbl
Time Base Lower Preliminary PPC440x5 CPU Core User’s Manual SPR 0x10C (User/Supervisor Read-Only); SPR 0x11C (Supervisor Write-Only) See Time Base on page 209. Figure 10-45. Time Base Lower (TBL) 0:31 Time Base Lower Low-order 32 bits of time base. regsumm440core.fm.
Page 514: Tbu
Time Base Upper PPC440x5 CPU Core User’s Manual Preliminary SPR 0x10D (User/Supervisor Read-Only); SPR 0x11D (Supervisor Write-Only) See Time Base on page 209. Figure 10-46. Time Base Upper (TBU) 0:31 Time Base Upper High-order 32 bits of time base. regsumm440core.fm.
Page 515: Tcr
Timer Control Register Preliminary PPC440x5 CPU Core User’s Manual SPR 0x154 Supervisor R/W See Timer Control Register (TCR) on page 215. FP FIE 0 1 2 3 4 5 6 7 8 9 10 Figure 10-47. Timer Control Register (TCR)
Page 516: Tsr
Timer Status Register PPC440x5 CPU Core User’s Manual Preliminary SPR 0x150 Supervisor Read/Clear See Timer Status Register (TSR) on page 216. 0 1 2 3 4 5 6 Figure 10-48. Timer Status Register (TSR) Enable Next Watchdog Timer Exception 0 Action on next Watchdog Timer exception is to set TSR[ENW] = 1.
Page 517: Usprg0
USPRG0 User Special Purpose Register General 0 Preliminary PPC440x5 CPU Core User’s Manual USPRG0 SPR 0x100 (User R/W) See Special Purpose Registers General (USPRG0, SPRG0–SPRG7) on page 75. Figure 10-49. User Special Purpose Register General (USPRG0) 0:31 General data Software value; no hardware usage.
Page 518: Xer
Integer Exception Register PPC440x5 CPU Core User’s Manual Preliminary SPR 0x001 User R/W See Integer Exception Register (XER) on page 72. 24 25 Figure 10-50. Integer Exception Register (XER) mtspr Summary Overflow Can be or by integer or auxiliary 0 No overﬂow has occurred.
Page 519: Appendix A. Instruction Summary
User’s Manual Preliminary PPC440x5 CPU Core Appendix A. Instruction Summary This appendix describes the various instruction formats, and lists all of the PPC440x5 instructions summa- rized alphabetically and by opcode. Appendix A.1 on page 519 illustrates the PPC440x5 instruction forms (allowed arrangements of fields within instructions).
Page 520: Instruction Fields
User’s Manual PPC440x5 CPU Core Preliminary A.1.1 Instruction Fields PPC440x5 instructions contain various combinations of the following fields, as indicated in the instruction format diagrams that follow the field definitions. Numbers, enclosed in parentheses, that follow the field names indicate bit positions; bit fields are indicated by starting and stopping bit positions separated by colons.
Page 521: Instruction Format Diagrams
User’s Manual Preliminary PPC440x5 CPU Core Used in rotate-and-mask instructions to specify the ending bit of a mask. NB (16:20) Speciﬁes the number of bytes to move in an immediate string load or store. OPCD (0:5) Primary opcode. Primary opcodes, in decimal, appear in the instruction format diagrams presented with individual instructions.
Page 522: I-Form
User’s Manual PPC440x5 CPU Core Preliminary A.1.2.1 I-Form OPCD Figure A-1. I Instruction Format A.1.2.2 B-Form OPCD AA LK 30 31 Figure A-2. B Instruction Format A.1.2.3 SC-Form OPCD 30 31 Figure A-3. SC Instruction Format A.1.2.4 D-Form OPCD OPCD...
Page 523: X-Form
User’s Manual Preliminary PPC440x5 CPU Core A.1.2.5 X-Form OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD Figure A-5. X Instruction Format instalfa.fm. September 12, 2002...
Page 524: Xl-Form
User’s Manual PPC440x5 CPU Core Preliminary A.1.2.6 XL-Form OPCD OPCD OPCD OPCD Figure A-6. XL Instruction Format A.1.2.7 XFX-Form OPCD SPRF OPCD DCRF OPCD OPCD SPRF OPCD DCRF Figure A-7. XFX Instruction Format A.1.2.8 XO-Form OPCD OPCD OPCD 21 22 Figure A-8.
Page 525: Table A-1. Ppc440X5 Instruction Syntax Summary
User’s Manual Preliminary PPC440x5 CPU Core Table A-1 summarizes the PPC440x5 instruction set, including required extended mnemonics. All mnemonics are listed alphabetically, without regard to whether the mnemonic is realized in hardware or soft- ware. When an instruction supports multiple hardware mnemonics (for example, b, ba, bl, bla are all forms of b), the instruction is alphabetized under the root form.
Page 526 User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed Add (IM 0) to (RA|0). addis RT, RA, IM Place result in RT. addme addme. CR[CR0] Add XER[CA], (RA), (-1).
Page 527 User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed bclr CTR if BO 2 = 0 Branch conditional to address in LR. BO, BI Using (LR) at entry to instruction,...
Page 528 User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed Decrement CTR. Branch if CTR 0 AND CR = 1. cr_bit bdnzt Extended mnemonic for bc 8,cr_bit,target Extended mnemonic for...
Page 529 User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed Decrement CTR. Branch if CTR = 0 AND CR = 1. cr_bit bdzt Extended mnemonic for bc 10,cr_bit,target Extended mnemonic for...
Page 530 User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed Branch if CR = 0 to address in CTR. cr_bit Extended mnemonic for bfctr bcctr 4,cr_bit cr_bit Extended mnemonic for...
Page 531 User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed Branch if greater than to address in LR. Use CR[CR0] if cr_field is omitted. bgtlr Extended mnemonic for [cr_field] bclr 12,4 cr_ﬁeld+1...
Page 532 User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed Branch if less than to address in CTR. Use CR[CR0] if cr_field is omitted. bltctr Extended mnemonic for [cr_field] bcctr 12,4 cr_ﬁeld+0...
Page 533 User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed Branch if not greater than to address in CTR. Use CR[CR0] if cr_field is omitted. bngctr Extended mnemonic for [cr_field] bcctr 4,4 cr_ﬁeld+1...
Page 534 User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed Branch if not summary overflow to address in CTR. Use CR[CR0] if cr_field is omitted. bnsctr Extended mnemonic for [cr_field] bcctr 4,4 cr_ﬁeld+3...
Page 535 User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed Branch if summary overflow to address in CTR. UseCR[CR0] if cr_field is omitted. bsoctr Extended mnemonic for [cr_field] bcctr 12,4 cr_ﬁeld+3...
Page 536 User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed Branch if unordered, to address in LR. bunlr Use CR[CR0] if cr_field is omitted. Extended mnemonic for [cr_field] bclr 12,4 cr_ﬁeld+3...
Page 537 User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed Compare Word Immediate. UseCR[CR0] if BF is omitted. cmpwi [BF,] RA, IM Extended mnemonic for cmpi BF,0,RA,IM cntlzw Count leading zeros in RS.
Page 538 User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed Read tag and data information from the data cache line selected using effective address bits 17:26. The effective address is cal- culated by (RA|0) + (RB).
Page 539 User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed extsb Extend the sign of byte (RS) 24:31 . RA, RS Place the result in RA. extsb. CR[CR0] extsh Extend the sign of halfword (RS) 16:31 .
Page 540 User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed Load halfword from EA = (RA|0) + EXTS(D) and sign extend, (RT) EXTS(MS(EA,2)). lhau RT, D(RA) Update the base address,...
Page 541 User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed Load consecutive bytes from EA=(RA|0)+(RB). Number of bytes n=XER[TBC]. Stack bytes into words in CEIL(n/4) consecutive registers starting with RT, to ((RT + CEIL(n/4) –...
Page 542 User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed machhw machhw. CR[CR0] prod (RA) (RB) 0:31 16:31 0:15 RT, RA, RB temp prod + (RT) machhwo XER[SO, OV] 0:32...
Page 543 User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed Move from CR to RT, mfcr (RT) (CR). Move from DCR to RT, mfdcr RT, DCRN (RT) (DCR(DCRN)). Move from MSR to RT,...
Page 544 User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed mfccr0 mfccr1 mfctr mfdac1 mfdac2 mfdbcr0 mfdbcr1 mfdbsr mfdccr mfdcwr mfdvc1 mfdvc2 mfesr mﬁac1 mfiac2 mfiac3 mfiac4 mﬁccr mﬁcdbdr mﬁvpr mﬂr...
Page 545 User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed Move register. (RS) (RT) Extended mnemonic for RT, RS or RT,RS,RS Extended mnemonic for CR[CR0] or. RT,RS,RS Synchronization. All instructions that precede...
Page 546 User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed mtccr0 mtccr1 mtctr mtdac1 mtdac2 mtdbcr0 mtdbcr1 mtdbsr mtdccr mtdcwr mtdvc1 mtdvc2 mtesr mtiac1 mtiac2 mtiac3 mtiac4 mticcr mticdbdr mtivpr mtlr Move to SPR SPRN.
Page 547 User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed Move to SPR from RS, mtspr SPRN, RS (SPR(SPRN)) (RS). mulchw RT, RA, RB (RT) 0 (RA) (RB) (signed) 16:31 0:15 mulchw.
Page 548 User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed nmacchws prod (RA) (RB) 0:31 16:31 0:15 nmacchws. CR[CR0] temp –prod + (RT) 0:32 0:31 RT, RA, RB if ((prod...
Page 549 User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed Return from interrupt. rﬁ (PC) (SRR0). (MSR) (SRR1). Return from machine check interrupt rfmci (PC) (MCSRR0). (MSR) (MCSRR1). rlwimi Rotate left word immediate, then insert according to mask.
Page 550 User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed Shift left immediate. (n < 32) (RA) 0:31-n (RS) n:31 slwi (RA) 32-n:31 Extended mnemonic for RA, RS, n rlwinm RA,RS,n,0,31 n Extended mnemonic for slwi.
Page 551 User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed Store halfword (RS) 16:31 in memory at EA = (RA|0) + EXTS(D). sthu RS, D(RA) Update the base address, (RA) Store halfword (RS) 16:31 in memory at EA = (RA|0) + (RB).
Page 552 User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed Subtract (RB) from (RA). (RT) (RB) + (RA) + 1. Extended mnemonic for subf RT,RB,RA Extended mnemonic for sub. CR[CR0] RT, RA, RB subf.
Page 553 User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed subfze subfze. CR[CR0] Subtract (RA) from zero with carry-in. RT, RA, RB (RT) (RA) + XER[CA]. subfzeo XER[SO, OV] Place carry-out in XER[CA].
Page 554 User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed tlbsync does not complete until all previous TLB-update instruc- tions executed by this processor have been received and com- tlbsync pleted by all other processors.
Page 555 User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed Trap unconditionally. Extended mnemonic for trap tw 31,0,0 Trap if (RA) equal to (RB). Extended mnemonic for tweq tw 4,RA,RB Trap if (RA) greater than or equal to (RB).
Page 556 User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed Trap if (RA) equal to EXTS(IM). Extended mnemonic for tweqi wi 4,RA,IM Trap if (RA) greater than or equal to EXTS(IM).
Page 557: Allocated Instruction Opcodes
User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Other Registers Mnemonic Operands Function Page Changed XOR (RS) with ( IM). xori RA, RS, IM Place result in RA. XOR (RS) with (IM xoris RA, RS, IM Place result in RA.
Page 558: Reserved Instruction Opcodes
User’s Manual PPC440x5 CPU Core Preliminary Table A-3 lists the reserved opcodes designated by PowerPC Book-E. The decimal value of the secondary opcode is shown in parentheses after the binary value. Table A-3. Preserved Opcodes Primary Extended Preserved PPC440x5 Opcode...
Page 559: Implemented Instructions Sorted By Opcode
User’s Manual Preliminary PPC440x5 CPU Core A.6 Implemented Instructions Sorted by Opcode Table A-5 on page 559 lists all of the instructions which have been implemented within the PPC440x5 core, sorted by primary and secondary opcode. These include defined, allocated, preserved, and reserved-nop class instructions (see Instruction Classes on page 53 for a more detailed description of each of these instruction classes).
Page 560 User’s Manual PPC440x5 CPU Core Preliminary Table A-5. PPC440x5 Instructions by Opcode (continued) Primary Secondary Form Mnemonic Operands Page Opcode Opcode mulhhw RT, RA, RB mulhhw. machhw machhw. 44 (556) RT, RA, RB machhwo machhwo. nmachhw nmachhw. 46 (558) RT, RA, RB nmachhwo nmachhwo.
Page 561 User’s Manual Preliminary PPC440x5 CPU Core Table A-5. PPC440x5 Instructions by Opcode (continued) Primary Secondary Form Mnemonic Operands Page Opcode Opcode macchws macchws. 236 (748) RT, RA, RB macchwso macchwso. nmacchws nmacchws. 238 (750) RT, RA, RB nmacchwso nmacchwso. mullhwu RT, RA, RB mullhwu.
Page 562 User’s Manual PPC440x5 CPU Core Preliminary Table A-5. PPC440x5 Instructions by Opcode (continued) Primary Secondary Form Mnemonic Operands Page Opcode Opcode BO, BI, target bcla target mcrf BF, BFA bclr BO, BI bclrl crnor BT, BA, BB rfmci rﬁ rfci...
Page 563 User’s Manual Preliminary PPC440x5 CPU Core Table A-5. PPC440x5 Instructions by Opcode (continued) Primary Secondary Form Mnemonic Operands Page Opcode Opcode subfc subfc. 8 (520) RT, RA, RB subfco subfco. addc addc. 10 (522) RT, RA, RB addco addco. mulhwu...
Page 564 User’s Manual PPC440x5 CPU Core Preliminary Table A-5. PPC440x5 Instructions by Opcode (continued) Primary Secondary Form Mnemonic Operands Page Opcode Opcode neg. 104 (616) RT, RA nego nego. lbzux RT, RA, RB RA, RS, RB nor. wrtee subfe subfe. 136 (648)
Page 565 User’s Manual Preliminary PPC440x5 CPU Core Table A-5. PPC440x5 Instructions by Opcode (continued) Primary Secondary Form Mnemonic Operands Page Opcode Opcode mullw mullw. 235 (747) RT, RA, RB mullwo mullwo. dcbtst RA,RB stbux RS, RA, RB icbt RA, RB add.
Page 566 User’s Manual PPC440x5 CPU Core Preliminary Table A-5. PPC440x5 Instructions by Opcode (continued) Primary Secondary Form Mnemonic Operands Page Opcode Opcode divw divw. 491 (1003) RT, RA, RB divwo divwo. mcrxr Reserved-nop lswx RT, RA, RB lwbrx RT, RA, RB RA, RS, RB srw.
Page 567 User’s Manual Preliminary PPC440x5 CPU Core Table A-5. PPC440x5 Instructions by Opcode (continued) Primary Secondary Form Mnemonic Operands Page Opcode Opcode icread RA, RB dcbz 1014 RA, RB RT, D(RA) lwzu RT, D(RA) RT, D(RA) lbzu RT, D(RA) RS, D(RA)
Page 568 User’s Manual PPC440x5 CPU Core Preliminary instalfa.fm. Page 568 of 589 September 12, 2002...
Page 569: Appendix B. Ppc440X5 Core Compiler Optimizations
User’s Manual Preliminary PPC440x5 CPU Core Appendix B. PPC440x5 Core Compiler Optimizations This appendix describes some potential optimizations for compilers. 1. Place target addresses (subroutine entry points) on cache line boundaries (32-bytes) 2. Up to ﬁve instructions between a load and a use of the load result. Assuming a data cache hit, the worst case scenario for the PPC440x5 core is ﬁve instructions between a load-use, in order to avoid any bub-...
Page 570 User’s Manual PPC440x5 CPU Core Preliminary If the CR-update is MAC or a 16 32 multiply, 1 to 3 instructions should be scheduled between the CR- update and the branch (0 or 1 instruction, depending on whether the CR-update pairs with the instruction...
Page 571 User’s Manual Preliminary PPC440x5 CPU Core Index bcctr bcctrl add. addc bcla addc. bclr addco bclrl addco. bctr adde bctrl adde. bdnz addeo bdnza addeo. bdnzf addi bdnzfa addic bdnzfl addic. bdnzfla addis bdnzflr addme bdnzflrl addme. bdnzl addmeo bdnzla addmeo.
Page 572 User’s Manual PPC440x5 CPU Core Preliminary bnelrl bfctr bnga bfctrl bngctr bngctrl bfla bngl bflr bngla bflrl bnglr bnglrl bgea bgectrl bnla bgel bnlctr bgela bnlctrl bgelr bnll bgelrl bnlla bgrctr bnllr bnllrl bgta bgtctr bnsa bgtctrl bnsctr bgtl bnsctrl...
Page 573 User’s Manual Preliminary PPC440x5 CPU Core btctrl coherence data cache btla coherency btlr instruction cache btlrl compare arithmetic buna logical bunctr Condition Register. See also CR bunctrl context synchronization bunl control bunla data cache bunlr instruction cache bunlrl conventions byte ordering...
Page 574 User’s Manual PPC440x5 CPU Core Preliminary data addressing modes DEAR data cache debug coherency debug cache data cache array organization and operation instruction cache data cache controller. See DCC debug events data cache line allocation on store miss data read PLB interface requests...
Page 575 User’s Manual Preliminary PPC440x5 CPU Core divwuo system call instruction divwuo. trap instructions dlmzb Exception Syndrome Register dlmzb. exception syndrome register DNV0–DNV3 Exceptions DTV0–DTV3 execution synchronization extended mnemonics debug events bctr applied to instructions that result in multiple storage bctrl...
Page 576 User’s Manual PPC440x5 CPU Core Preliminary bnlctr bfla bnlctrl bflr bnll bflrl bnlla bnllr bgea bnllrl bgectr bgectrl bnsa bgel bnsctr bgela bnsctrl bgelr bnsl bgelrl bnsla bnslr bgta bnslrl bgtctr bgtctrl bnua bgtl bnuctr bgtla bnuctrl bgtlr bnul bgtlrl...
Page 577 User’s Manual Preliminary PPC440x5 CPU Core crclr srwi. crmove crnot sub. crset subc extlwi subc. extlwi. subco extrwi subco. extrwi. subi for addi subic for addic subic. for addic. subis for addis subo for bc, bca, bcl, bcla subo. for bcctr, bcctrl...
Page 578 User’s Manual PPC440x5 CPU Core Preliminary implicit update imprecise interrupts inslwi fixed interval timer inslwi. fixed interval timer interrupt insrwi Fixed-Interval Timer interrupt insrwi. floating point interrupt unavailable interrupts instruction floating-point load and store instructions, exception priori- ties for add.
Page 579 User’s Manual Preliminary PPC440x5 CPU Core crandc macchwsu creqv macchwu crnand machhw crnor machhwsu cror machhwu crorc maclhw crxor maclhws dcbf maclhwu dcbi mbar dcbst mcrf dcbt mcrxr dcbtst mfcr dcbz mfdcr dccci mfmsr dcread mfspr divw msync divw. mtcrf...
Page 580 User’s Manual PPC440x5 CPU Core Preliminary rlwimi tlbsync rlwimi. tlbwe rlwinm rlwinm. rlwnm wrtee rlwnm. wrteei xori slw. instruction address compare See also IAC sraw instruction addressing modes sraw. instruction cache array organization and operation srawi instruction cache coherency srawi.
Page 581 User’s Manual Preliminary PPC440x5 CPU Core allocated preserved instruction opcodes instructions preserved, exception priorities for all other, exception priorities for privileged allocated (other), exception priorities for privileged instructions, exception priorities for allocated instruction opcodes pseudocode operator precedence allocated load and store, exception priorities for...
Page 582 User’s Manual PPC440x5 CPU Core Preliminary Decrementer IVPR External Input Fixed-Interval Timer Floating-Point Unavailable Instruction TLB Error Machine Check Program interrupt lbzu System Call lbzx Watchdog Timer interrupt (IRPT) debug events lhau interrupt and exception handling registers lhax lhbrx interrupt classes...
Page 583 User’s Manual Preliminary PPC440x5 CPU Core mcrf neg. mcrxr nego MCSR nego. MCSRR0 nmacchw MCSRR1 nmacchws memory coherence required nmachhw memory management unit nmachhws memory management. See also MMU nmaclhw memory map nmaclhws memory organization non-critical interrupts mfcr mfdcr mfmsr nor.
Page 584 User’s Manual PPC440x5 CPU Core Preliminary privileged mode IAC1–IAC4 privileged operation ICDBDR privileged SPRs ICDBTRH problem state ICDBTRL processor control instruction summary interrupt processing processor control instructions INV0–INV3 CR logical ITV0–ITV3 register management IVLIM synchronization IVOR0–IVOR15 system linkage IVPR processor control registers...
Page 585 User’s Manual Preliminary PPC440x5 CPU Core sthux rfmci sthx rlwimi stmw rlwimi. storage access ordering rlwinm storage attributes rlwinm. caching inhibited rlwnm endian rlwnm. guarded rotlw Memory Coherence Required rotlw. supported combinations rotlwi user-definable (U0–U3) rotlwi. write-through required rotrwi storage control instruction summary rotrwi.
Page 586: Subi Subic Subic
User’s Manual PPC440x5 CPU Core Preliminary subfze subfze. subfzeo subfzeo. subi subic subic. subis subo overview subo. shadow arrays supervisor state TLB management instructions synchronization overview architectural references tlbre context tlbsx execution tlbsx. storage tlbsync synchronous interrupt class tlbwe synonyms, instruction cache...
Page 587 User’s Manual Preliminary PPC440x5 CPU Core U, V, W U0–U3 storage attributes unconditional (UDE) debug events units memeory management user mode USPRG0 W storage attribute Watchdog Timer interrupt watchdog timer interrupts write-through required writing the time base wrtee wrteei carry (CA) field...
Page 588 User’s Manual PPC440x5 CPU Core Preliminary ppc440x5IX.fm. Page 588 of 583 September 12, 2002...
Page 589 User’s Manual Preliminary PPC440x5 CPU Core Revision Log Revision Date Contents of Modiﬁcation 7/25/2002 Reformatted to division standard template, no content revisions. Content and format revisions summarized by chapter: Ch. 2: CCR1 updated Ch. 4: CCR0 and CCR1 updated. Sections on data cache parity insertion and simulating parity errors revised.

IBM PPC440X5 CPU Core User Manual

Table of Contents

Figures

Tables

About this Book

1 Overview

2 Programming Model

3 Initialization

4 Instruction and Data Caches

5 Memory Management

6 Interrupts and Exceptions

7 Timer Facilities

8 Debug Facilities

9 Instruction Set

10 Register Summary

Appendix A. Instruction Summary

Appendix B. Ppc440X5 Core Compiler Optimizations

Quick Links

Chapters

Related Manuals for IBM PPC440X5 CPU Core

Summary of Contents for IBM PPC440X5 CPU Core