Figure 4-1. Instruction Flow - IBM PowerPC 405GP User Manual

Figure 4-1 shows the relationships between the ICU and the instruction pipeline.
Instructions from Memory
I
to Memory
-+-
i
Addresses
Tag Instruction
Bypass Path
Arrays
Arrays
I
Address es from Fetcher
PFB1
PFBO
Instruc tion Queue
Decode
~
I
Execute
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Figure 4-1. Instruction Flow
4.1.1
leu
Operations
Instructions from cachable memory regions are copied into the instruction cache array. The fetcher
can access instructions much more quickly from a cache array than from memory. Cache lines are
loaded either target-ward-first or sequentially. Target-ward-first fills start at the requested word,
continue to the end of the line, and then wrap to fill the remaining words at the beginning of the line.
Sequential fills start at the first word of the cache line and proceed sequentially to the last word of the
line.
The bypass path handles instructions in cache-inhibited memory and improves performance during
line fill operations. If a request from the fetcher obtains an entire line from memory, the queue does
not have to wait for the entire line to reach the cache. The target word (the word requested by the
fetcher) is sent on the bypass path to the queue while the line fill proceeds, even if the selected line fill
order is not target-ward-first.
Cache line fills always run to completion, even if the instruction stream branches away from the rest of
the line. As requested instructions are received, they go to the fetcher from the fill register before the
line fills in the cache. The filled line is always placed in the ICU; if an external memory subsystem
error occurs during the fill, the line is not written to the cache. During a clock cycle, the ICU can send
two instruction to the fetcher.
Preliminary
Cache Operations 4-3