IBM PPC440X5 CPU Core Manuals

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IBM PPC440X5 CPU Core User Manual

IBM PPC440X5 CPU Core User Manual (590 pages)

CPU Core

Brand: IBM | Category: Computer Hardware | Size: 6.91 MB

Table of Contents

Table of Contents

3
- Figures
  
  15
- Tables
  
  19
- About this Book
  
  23
  - Related Publications
    25
- 1 Overview
  
  27
  - Ppc440X5 Features
    27
  - The Ppc440X5 as a Powerpc Implementation
    29
  - Ppc440X5 Organization
    30
    
    Figure 1-1. PPC440 Core Block Diagram
    30
    
    Superscalar Instruction Unit
    30
    
    Execution Pipelines
    31
    
    Instruction and Data Cache Controllers
    31
    
    Instruction Cache Controller (ICC)
    31
    
    Data Cache Controller (DCC)
    32
    
    Memory Management Unit (MMU)
    32
    
    Debug Facilities
    34
    
    Debug Modes
    34
    
    Timers
    34
    
    Development Tool Support
    35
  - Core Interfaces
    35
    
    Auxiliary Processor Unit (APU) Port
    36
    
    Device Control Register (DCR) Interface
    36
    
    Processor Local Bus (PLB)
    36
    
    JTAG Port
    37
- 2 Programming Model
  
  39
- 3 Initialization
  
  85
- 4 Instruction and Data Caches
  
  95
- 5 Memory Management
  
  133
  - MMU Overview
    133
    
    Support for Powerpc Book-E MMU Architecture
    133
  - Translation Lookaside Buffer
    134
  - Table 5-1. TLB Entry Fields
    135
  - Page Identification
    138
    
    Address Space Identifier Convention
    138
    
    Virtual Address Formation
    138
    
    TLB Match Process
    139
  - Address Translation
    140
  - Figure 5-1. Virtual Address to TLB Entry Match Process
    140
  - Table 5-2. Page Size and Effective Address to EPN Comparison
    140
  - Figure 5-2. Effective-To-Real Address Translation Flow
    141
  - Access Control
    142
    
    Execute Access
    142
    
    Table 5-3. Page Size and Real Address Formation
    142
    
    Write Access
    142
    
    Access Control Applied to Cache Management Instructions
    143
    
    Read Access
    143
    
    Table 5-4. Access Control Applied to Cache Management Instructions
    144
  - Storage Attributes
    145
    
    Caching Inhibited (I)
    145
    
    Write-Through (W)
    145
    
    Endian (E)
    146
    
    Guarded (G)
    146
    
    Memory Coherence Required (M)
    146
    
    Supported Storage Attribute Combinations
    147
    
    User-Definable (U0-U3)
    147
  - Storage Control Registers
    147
    
    Figure 5-3. Memory Management Unit Control Register (MMUCR)
    148
    
    Memory Management Unit Control Register (MMUCR)
    148
    
    Process ID (PID)
    151
  - Shadow TLB Arrays
    151
  - Figure 5-4. Process ID (PID)
    151
  - TLB Management Instructions
    152
    
    TLB Read/Write Instructions (Tlbre/Tlbwe)
    153
    
    TLB Search Instruction (Tlbsx[.])
    153
    
    TLB Sync Instruction (Tlbsync)
    154
  - Page Reference and Change Status Management
    154
  - Figure 5-5. TLB Entry Word Definitions
    154
  - TLB Parity Operations
    155
    
    Reading TLB Parity Bits with Tlbre
    155
    
    Simulating TLB Parity Errors for Software Testing
    156
- 6 Interrupts and Exceptions
  
  159
- 7 Timer Facilities
  
  209
  - Time Base
    209
  - Figure 7-1. Relationship of Timer Facilities to the Time Base
    209
    
    Figure 7-2. Time Base Lower (TBL)
    210
    
    Figure 7-3. Time Base Upper (TBU)
    210
    
    Reading the Time Base
    210
    
    Writing the Time Base
    210
  - Decrementer (DEC)
    211
  - Figure 7-4. Decrementer (DEC)
    211
  - Fixed Interval Timer (FIT)
    212
  - Figure 7-5. Decrementer Auto-Reload (DECAR)
    212
  - Table 7-1. Fixed Interval Timer Period Selection
    212
  - Watchdog Timer
    213
  - Table 7-2. Watchdog Timer Period Selection
    213
  - Table 7-3. Watchdog Timer Exception Behavior
    214
  - Timer Control Register (TCR)
    215
  - Figure 7-6. Watchdog State Machine
    215
  - Timer Status Register (TSR)
    216
  - Figure 7-7. Timer Control Register (TCR)
    216
  - Freezing the Timer Facilities
    217
  - Selection of the Timer Clock Source
    217
  - Figure 7-8. Timer Status Register (TSR)
    217
- 8 Debug Facilities
  
  219
  - Support for Development Tools
    219
  - Debug Modes
    219
    
    Internal Debug Mode
    219
    
    Debug Wait Mode
    220
    
    External Debug Mode
    220
    
    Trace Debug Mode
    221
  - Debug Events
    221
  - Table 8-1. Debug Events
    221
    
    IAC Debug Event Fields
    222
    
    Instruction Address Compare (IAC) Debug Event
    222
    
    IAC Debug Event Processing
    225
    
    Table 8-2. IAC Range Mode Auto-Toggle Summary
    225
    
    DAC Debug Event Fields
    226
    
    Data Address Compare (DAC) Debug Event
    226
    
    DAC Debug Event Processing
    229
    
    DAC Debug Events Applied to Instructions that Result in Multiple Storage Accesses
    230
    
    DAC Debug Events Applied to Various Instruction Types
    230
    
    Data Value Compare (DVC) Debug Event
    231
    
    DVC Debug Event Fields
    232
    
    DVC Debug Event Processing
    233
    
    DVC Debug Events Applied to Instructions that Result in Multiple Storage Accesses
    233
    
    DVC Debug Events Applied to Various Instruction Types
    233
    
    Branch Taken (BRT) Debug Event
    234
    
    Trap (TRAP) Debug Event
    234
    
    Instruction Complete (ICMP) Debug Event
    235
    
    Return (RET) Debug Event
    235
    
    Interrupt (IRPT) Debug Event
    236
    
    Debug Event Summary
    237
    
    Table 8-3. Debug Event Summary
    237
    
    Unconditional Debug Event (UDE)
    237
  - Debug Reset
    238
  - Debug Timer Freeze
    238
  - Debug Registers
    238
    
    Debug Control Register 0 (DBCR0)
    239
    
    Figure 8-1. Debug Control Register 0 (DBCR0)
    239
    
    Debug Control Register 1 (DBCR1)
    240
    
    Figure 8-2. Debug Control Register 1 (DBCR1)
    240
    
    Debug Control Register 2 (DBCR2)
    243
    
    Figure 8-3. Debug Control Register 2 (DBCR2)
    243
    
    Debug Status Register (DBSR)
    244
    
    Figure 8-4. Debug Status Register (DBSR)
    244
    
    Instruction Address Compare Registers (IAC1-IAC4)
    245
    
    Data Address Compare Registers (DAC1-DAC2)
    246
    
    Data Value Compare Registers (DVC1-DVC2)
    246
    
    Figure 8-5. Instruction Address Compare Registers (IAC1-IAC4)
    246
    
    Figure 8-6. Data Address Compare Registers (DAC1-DAC2)
    246
    
    Figure 8-7. Data Value Compare Registers (DVC1-DVC2)
    246
    
    Debug Data Register (DBDR)
    247
    
    Figure 8-8. Debug Data Register (DBDR)
    247
- 9 Instruction Set
  
  249
  - Table 9-1. Instruction Categories
    249
    
    Instruction Formats
    250
    
    Instruction Set Portability
    250
    
    Table 9-2. Allocated Instructions
    250
    
    Pseudocode
    251
    
    Operator Precedence
    253
    
    Register Usage
    253
    
    Table 9-3. Operator Precedence
    253
    
    Alphabetical Instruction Listing
    254
    
    Add
    255
    
    Addc
    256
    
    Adde
    257
    
    Addi
    258
    
    Table 9-4. Extended Mnemonics for Addi
    258
    
    Addic
    259
    
    Table 9-5. Extended Mnemonics for Addic
    259
    
    Addic
    260
    
    Table 9-6. Extended Mnemonics for Addic
    260
    
    Addis
    261
    
    Table 9-7. Extended Mnemonics for Addis
    261
    
    Addme
    262
    
    Addze
    263
    
    And
    264
    
    Andc
    265
    
    Andi
    266
    
    Andis
    267
    
    Table 9-8. Extended Mnemonics for Bc, Bca, Bcl, Bcla
    270
    
    Bcctr
    275
    
    Table 9-9. Extended Mnemonics for Bcctr, Bcctrl
    275
    
    Bclr
    278
    
    Table 9-10. Extended Mnemonics for Bclr, Bclrl
    279
    
    Cmp
    282
    
    Table 9-11. Extended Mnemonics for Cmp
    282
    
    Cmpi
    283
    
    Table 9-12. Extended Mnemonics for Cmpi
    283
    
    Cmpl
    284
    
    Table 9-13. Extended Mnemonics for Cmpl
    284
    
    Cmpli
    285
    
    Table 9-14. Extended Mnemonics for Cmpli
    285
    
    Cntlzw
    286
    
    Crand
    287
    
    Crandc
    288
    
    Creqv
    289
    
    Table 9-15. Extended Mnemonics for Creqv
    289
    
    Crnand
    290
    
    Crnor
    291
    
    Table 9-16. Extended Mnemonics for Crnor
    291
    
    Cror
    292
    
    Table 9-17. Extended Mnemonics for Cror
    292
    
    Crorc
    293
    
    Crxor
    294
    
    Table 9-18. Extended Mnemonics for Crxor
    294
    
    Dcba
    295
    
    Dcbf
    296
    
    Dcbi
    297
    
    Dcbst
    298
    
    Dcbt
    299
    
    Dcbtst
    300
    
    Dcbz
    302
    
    DCCCI
    304
    
    Dcread
    305
    
    Divw
    307
    
    Divwu
    308
    
    Dlmzb
    309
    
    Eqv
    310
    
    Extsb
    311
    
    Extsh
    312
    
    Icbi
    313
  - Icbt
    314
  - ICCCI
    316
  - Icread
    317
  - Isel
    319
  - Isync
    320
  - Lbz
    321
  - Lbzu
    322
  - Lbzux
    323
  - Lbzx
    324
  - Lha
    325
  - Lhau
    326
  - Lhaux
    327
  - Lhax
    328
  - Lhbrx
    329
  - Lhz
    330
  - Lhzu
    331
  - Lhzux
    332
  - Lhzx
    333
  - Lmw
    334
  - Lswi
    335
  - Lswx
    337
  - Lwarx
    339
  - Lwbrx
    340
  - Lwz
    341
  - Lwzu
    342
  - Lwzux
    343
  - Lwzx
    344
  - Macchw
    345
  - Macchws
    346
  - Macchwsu
    347
  - Macchwu
    348
  - Machhw
    349
  - Machhws
    350
  - Machhwsu
    351
  - Machhwu
    352
  - Maclhw
    353
  - Maclhws
    354
  - Maclhwsu
    355
  - Maclhwu
    356
  - Mbar
    357
  - Mcrf
    358
  - Mcrxr
    359
  - Mfcr
    360
  - Mfdcr
    361
  - Mfmsr
    362
  - Mfspr
    363
  - Table 9-19. Extended Mnemonics for Mfspr
    364
  - Msync
    366
  - Mtcrf
    367
  - Table 9-20. FXM Bit Field Correspondence
    367
  - Table 9-21. Extended Mnemonics for Mtcrf
    367
  - Mtdcr
    368
  - Mtmsr
    369
  - Mtspr
    370
  - Table 9-22. Extended Mnemonics for Mtspr
    371
  - Mulchw
    373
  - Mulchwu
    374
  - Mulhhw
    375
  - Mulhhwu
    376
  - Mulhw
    377
  - Mulhwu
    378
  - Mullhw
    379
  - Mullhwu
    380
  - Mulli
    381
  - Mullw
    382
  - Nand
    383
  - Neg
    384
  - Nmacchw
    385
  - Nmacchws
    386
  - Nmachhw
    387
  - Nmachhws
    388
  - Nmaclhw
    389
  - Nmaclhws
    390
  - Nor
    391
  - Table 9-23. Extended Mnemonics for Nor, nor
    391
  - Table 9-24. Extended Mnemonics for Or, or
    392
  - Orc
    393
  - Ori
    394
  - Table 9-25. Extended Mnemonics for Ori
    394
  - Oris
    395
  - Rfci
    396
  - Rfi
    397
  - Rfmci
    398
  - Rlwimi
    399
  - Table 9-26. Extended Mnemonics for Rlwimi, Rlwimi
    399
  - Rlwinm
    400
  - Table 9-27. Extended Mnemonics for Rlwinm, Rlwinm
    400
  - Rlwnm
    403
  - Table 9-28. Extended Mnemonics for Rlwnm, Rlwnm
    403
  - Slw
    405
  - Sraw
    406
  - Srawi
    407
  - Srw
    408
  - Stb
    409
  - Stbu
    410
  - Stbux
    411
  - Stbx
    412
  - Sth
    413
  - Sthbrx
    414
  - Sthu
    415
  - Sthux
    416
  - Sthx
    417
  - Stmw
    418
  - Stswi
    419
  - Stswx
    421
  - Stw
    422
  - Stwbrx
    423
  - Stwcx
    424
    
    Stwu
    426
    
    Stwux
    427
    
    Stwx
    428
    
    Sub
    429
    
    Subf
    429
    
    Table 9-29. Extended Mnemonics for Subf, Subf., Subfo, Subfo
    429
    
    Subfc
    430
    
    Table 9-30. Extended Mnemonics for Subfc, Subfc., Subfco, Subfco
    430
    
    Subfe
    431
    
    Subfic
    432
    
    Subfme
    433
    
    Subfze
    434
    
    Tlbre
    435
    
    Tlbsx
    437
    
    Tlbsync
    438
    
    Tlbwe
    439
    
    Table 9-31. Extended Mnemonics for Tw
    441
    
    Trap
    441
    
    Tweq
    441
    
    Twge
    441
    
    Twgt
    441
    
    Twle
    441
    
    Twlgt
    441
    
    Twlle
    441
    
    Twllt
    441
    
    Twlng
    441
    
    Twng
    442
    
    Twnl
    442
    
    Twi
    443
    
    Table 9-32. Extended Mnemonics for Twi
    444
    
    Tweqi
    444
    
    Twgei
    444
    
    Twgti
    444
    
    Twlei
    444
    
    Twlgei
    444
    
    Twlgti
    444
    
    Twllei
    444
    
    Twllti
    444
    
    Twlngi
    444
    
    Twnli
    445
    
    Wrtee
    446
    
    Wrteei
    447
    
    Xor
    448
    
    Xori
    449
    
    Xoris
    450
- 10 Register Summary
  
  451
  - Register Categories
    451
  - Table 10-1. Register Categories
    452
  - Table 10-2. Special Purpose Registers Sorted by SPR Number
    454
  - Reserved Fields
    457
  - Device Control Registers
    457
  - Alphabetical Register Listing
    459
    
    Ccr0
    460
    
    Figure 10-1. Core Configuration Register 0 (CCR0)
    460
    
    Ccr1
    462
    
    Figure 10-2. Core Configuration Register 1 (CCR1)
    462
    
    Figure 10-3. Condition Register (CR)
    464
    
    Csrr0
    465
    
    Figure 10-4. Critical Save/Restore Register 0 (CSRR0)
    465
    
    Csrr1
    466
    
    Figure 10-5. Critical Save/Restore Register 1 (CSRR1)
    466
    
    Ctr
    467
    
    Figure 10-6. Count Register (CTR)
    467
    
    Dac1-Dac2
    468
    
    Figure 10-7. Data Address Compare Registers (DAC1-DAC2)
    468
    
    Dbcr0
    469
    
    Figure 10-8. Debug Control Register 0 (DBCR0)
    469
    
    Dbcr1
    471
    
    Figure 10-9. Debug Control Register 1 (DBCR1)
    471
    
    Dbcr2
    473
    
    Figure 10-10. Debug Control Register 2 (DBCR2)
    473
    
    Dbdr
    475
    
    Figure 10-11. Debug Data Register (DBDR)
    475
    
    Dbsr
    476
    
    Figure 10-12. Debug Status Register (DBSR)
    476
    
    Dcdbtrh
    478
    
    Figure 10-13. Data Cache Debug Tag Register High (DCDBTRH)
    478
    
    Dcdbtrl
    479
    
    Figure 10-14. Data Cache Debug Tag Register Low (DCDBTRL)
    479
    
    Dear
    480
    
    Figure 10-15. Data Exception Address Register (DEAR)
    480
    
    Dec
    481
    
    Figure 10-16. Decrementer (DEC)
    481
    
    Decar
    482
    
    Figure 10-17. Decrementer Auto-Reload (DECAR)
    482
    
    Dnv0-Dnv3
    483
    
    Figure 10-18. Data Cache Normal Victim Registers (DNV0-DNV3)
    483
    
    Dtv0-Dtv3
    484
    
    Figure 10-19. Data Cache Transient Victim Registers (DTV0-DTV3)
    484
    
    Dvc1-Dvc2
    485
    
    Figure 10-20. Data Value Compare Registers (DVC1-DVC2)
    485
    
    Dvlim
    486
    
    Figure 10-21. Data Cache Victim Limit (DVLIM)
    486
    
    Esr
    487
    
    Figure 10-22. Exception Syndrome Register (ESR)
    487
    
    Figure 10-23. General Purpose Registers (R0-R31)
    489
    
    Gpr0-Gpr31
    489
    
    Figure 10-24. Instruction Address Compare Registers (IAC1-IAC4)
    490
    
    Iac1-Iac4
    490
    
    Figure 10-25. Instruction Cache Debug Data Register (ICDBDR)
    491
    
    Icdbdr
    491
    
    Figure 10-26. Instruction Cache Debug Tag Register High (ICDBTRH)
    492
    
    Icdbtrh
    492
    
    Figure 10-27. Instruction Cache Debug Tag Register Low (ICDBTRL)
    493
    
    Icdbtrl
    493
    
    Figure 10-28. Instruction Cache Normal Victim Registers (INV0-INV3)
    494
    
    Inv0-Inv3
    494
    
    Figure 10-29. Instruction Cache Transient Victim Registers (ITV0-ITV3)
    495
    
    Itv0-Itv3
    495
    
    Figure 10-30. Instruction Cache Victim Limit (IVLIM)
    496
    
    Ivlim
    496
    
    Figure 10-31. Interrupt Vector Offset Registers (IVOR0-IVOR15)
    497
    
    Ivor0-Ivor15
    497
    
    Table 10-3. Interrupt Types Associated with each IVOR
    497
    
    Figure 10-32. Interrupt Vector Prefix Register (IVPR)
    498
    
    Ivpr
    498
    
    Figure 10-33. Link Register (LR)
    499
    
    Figure 10-34. Machine Check Status Register (MCSR)
    500
    
    Mcsr
    500
    
    Figure 10-35. Machine Check Save/Restore Register 0 (MCSRR0)
    501
    
    Mcsrr0
    501
    
    Figure 0-2. Machine Check Save/Restore Register 1 (MCSRR1)
    502
    
    Mcsrr1
    502
    
    Figure 10-36. Memory Management Unit Control Register (MMUCR)
    503
    
    Mmucr
    503
    
    Figure 10-37. Machine State Register (MSR)
    504
    
    Msr
    504
    
    Figure 10-38. Process ID (PID)
    506
    
    Pid
    506
    
    Figure 10-39. Processor Identification Register (PIR)
    507
    
    Pir
    507
    
    Figure 10-40. Processor Version Register (PVR)
    508
    
    Pvr
    508
    
    Figure 10-41. Reset Configuration
    509
    
    Rstcfg
    509
    
    Figure 10-42. Special Purpose Registers General (SPRG0-SPRG7)
    510
    
    Sprg0-Sprg7
    510
    
    Figure 10-43. Save/Restore Register 0 (SRR0)
    511
    
    Srr0
    511
    
    Figure 10-44. Save/Restore Register 1 (SRR1)
    512
    
    Srr1
    512
    
    Figure 10-45. Time Base Lower (TBL)
    513
    
    Tbl
    513
    
    Figure 10-46. Time Base Upper (TBU)
    514
    
    Tbu
    514
    
    Figure 10-47. Timer Control Register (TCR)
    515
    
    Tcr
    515
    
    Figure 10-48. Timer Status Register (TSR)
    516
    
    Tsr
    516
    
    Figure 10-49. User Special Purpose Register General (USPRG0)
    517
    
    Usprg0
    517
    
    Figure 10-50. Integer Exception Register (XER)
    518
    
    Xer
    518
- Appendix A. Instruction Summary
  
  519
  - Instruction Formats
    519
    
    Instruction Fields
    520
    
    Instruction Format Diagrams
    521
    
    B-Form
    522
    
    D-Form
    522
    
    Figure A-1. I Instruction Format
    522
    
    Figure A-2. B Instruction Format
    522
    
    Figure A-3. SC Instruction Format
    522
    
    Figure A-4. D Instruction Format
    522
    
    I-Form
    522
    
    SC-Form
    522
    
    Figure A-5. X Instruction Format
    523
    
    X-Form
    523
    
    M-Form
    524
    
    XFX-Form
    524
    
    XL-Form
    524
    
    XO-Form
    524
  - Alphabetical Summary of Implemented Instructions
    524
  - Figure A-6. XL Instruction Format
    524
  - Figure A-7. XFX Instruction Format
    524
  - Figure A-8. XO Instruction Format
    524
  - Figure A-9. M Instruction Format
    524
  - Table A-1. Ppc440X5 Instruction Syntax Summary
    525
  - Allocated Instruction Opcodes
    557
  - Preserved Instruction Opcodes
    557
  - Table A-2. Allocated Opcodes
    557
  - Reserved Instruction Opcodes
    558
  - Table A-3. Preserved Opcodes
    558
  - Table A-4. Reserved-Nop Opcodes
    558
  - Implemented Instructions Sorted by Opcode
    559
  - Table A-5. Ppc440X5 Instructions by Opcode
    559
- Appendix B. Ppc440X5 Core Compiler Optimizations
  
  569
, ,Twnli445

577
- Subi Subic Subic
  586
- Subis Subo Subo
  586
- Twgle
  586

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