Read Access; Access Control Applied To Cache Management Instructions - IBM PPC440X5 CPU Core User Manual

Preliminary
store operation is attempted in user mode to a page for which the UW access control bit is 0, then a Write
Access Control exception occurs. If the instruction is an stswx with string length 0, then no interrupt is
taken and no operation is performed (see Access Control Applied to Cache Management Instructions on
page 143). For all other store operations, execution of the instruction is suppressed and a Data Storage
interrupt is taken.
Note that although the dcbi cache management instruction is a store-class instruction, its execution is
privileged and thus will not cause a Data Storage interrupt if execution of it is attempted in user mode (a
Privileged Instruction exception type Program interrupt will occur instead).
• Supervisor mode (MSR[PR] = 0)
Store operations (including the store-class cache management instructions dcbz and dcbi) are permitted
to a page in storage while in supervisor mode if the SW access control bit for that page is equal to 1. If
execution of a store operation is attemped in supervisor mode to a page for which the SW access control
bit is 0, then a Write Access Control exception occurs. If the instruction is an stswx with string length 0,
then no interrupt is taken and no operation is performed (see Access Control Applied to Cache Manage-
ment Instructions on page 143). For all other store operations, execution of the instruction is suppressed
and a Data Storage interrupt is taken.

5.5.3 Read Access

The UR or SR bit of a TLB entry controls read access to a page, depending on the operating mode (user or
supervisor) of the processor.
• User mode (MSR[PR] = 1)
Load operations (including the load-class cache management instructions dcbst, dcbf, dcbt, dcbtst,
icbi, and icbt) are permitted from a page in storage while in user mode if the UR access control bit for
that page is equal to 1. If execution of a load operation is attempted in user mode to a page for which the
UR access control bit is 0, then a Read Access Control exception occurs. If the instruction is a load (not
including lswx with string length 0) or is a dcbst, dcbf, or icbi, then execution of the instruction is sup-
pressed and a Data Storage interrupt is taken. On the other hand, if the instruction is an lswx with string
length 0, or is a dcbt, dcbtst, or icbt, then no interrupt is taken and no operation is performed (see
Access Control Applied to Cache Management Instructions below).
• Supervisor mode (MSR[PR] = 0)
Load operations (including the load-class cache management instructions dcbst, dcbf, dcbt, dcbtst,
icbi, and icbt) are permitted from a page in storage while in supervisor mode if the SR access control bit
for that page is equal to 1. If execution of a load operation is attempted in supervisor mode to a page for
which the SR access control bit is 0, then a Read Access Control exception occurs. If the instruction is a
load (not including lswx with string length 0) or is a dcbst, dcbf, or icbi, then execution of the instruction
is suppressed and a Data Storage interrupt is taken. On the other hand, if the instruction is an lswx with
string length 0, or is a dcbt, dcbtst, or icbt, then no interrupt is taken and no operation is performed (see
Access Control Applied to Cache Management Instructions below).

5.5.4 Access Control Applied to Cache Management Instructions

This section summarizes how each of the cache management instructions is affected by the access control
mechanism.
mmu.fm.
September 12, 2002
User's Manual
PPC440x5 CPU Core
Page 143 of 589