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User's Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
3.4.1.4 Instruction-Cache Flash Invalidation
The instruction cache is automatically invalidated when the 750GX is powered up and during a hard reset.
However, a soft reset does not automatically invalidate the instruction cache. Software must use the HID0
instruction-cache flash invalidate bit (HID0[ICFI]) if instruction-cache invalidation is desired after a soft reset.
Once HID0[ICFI] is set through an mtspr operation, the 750GX automatically clears this bit in the next clock
cycle (provided that the instruction cache is enabled in the HID0 Register).
Note: Some PowerPC microprocessors accomplish instruction-cache flash invalidation by setting and clear-
ing HID0[ICFI] with two consecutive mtspr instructions (that is, the bit is not automatically cleared by the
microprocessor). Software that has this sequence of operations does not need to be changed to run on the
750GX.
3.4.1.5 Enabling and Disabling the Instruction Cache
The instruction cache can be enabled or disabled through the use of the instruction-cache enable bit,
HID0[ICE]. HID0[ICE] is cleared on power-up, disabling the instruction cache.
When the instruction cache is in the disabled state (HID[ICE] = 0), the cache tag state bits are ignored, and all
instruction fetches are propagated to the L2 cache or 60x bus as single-beat transactions. Note that the CI
signal always reflects the state of the caching-inhibited memory/cache access attribute (the I bit) independent
of the state of HID0[ICE]. Also note that disabling the instruction cache does not affect the translation logic;
translation for instruction accesses is controlled by MSR[IR].
The setting of the ICE bit must be preceded by an instruction sync (isync) instruction to prevent the cache
from being enabled or disabled in the middle of an instruction fetch. In addition, the cache must be globally
flushed before it is disabled to prevent coherency problems when it is re-enabled. The Instruction Cache
Block Invalidate (icbi) instruction is not affected by disabling the instruction cache.
3.4.1.6 Locking the Instruction Cache
The contents of the instruction cache can be locked by setting the instruction-cache lock bit, HID0[ILOCK]. An
instruction fetch that hits in a locked instruction cache is serviced by the cache. However, all accesses that
miss in the locked cache are propagated to the L2 cache or 60x bus as single-beat transactions. Note that the
CI signal always reflects the state of the caching-inhibited memory/cache access attribute (the I bit) indepen-
dent of the state of HID0[ILOCK].
The setting of the ILOCK bit must be preceded by an isync instruction to prevent the instruction cache from
being locked during an instruction fetch.
3.4.2 Cache-Control Instructions
The PowerPC Architecture defines instructions for controlling both the instruction and data caches (when
they exist). The cache-control instructions, dcbt, dcbtst, dcbz, dcbst, dcbf, dcbi, and icbi, are intended for
the management of the local L1 and L2 caches. The 750GX interprets the cache-control instructions as if they
pertain only to its own L1 or L2 caches. These instructions are not intended for managing other caches in the
system (except to the extent necessary to maintain coherency).
The 750GX does not snoop cache-control instruction broadcasts, except for Data Cache Block Zero (dcbz)
when M = 1. The dcbz instruction is the only cache-control instruction that causes a broadcast on the 60x bus
(when M = 1) to maintain coherency. All other data cache-control instructions (dcbi, dcbf, dcbst, and dcbz)
gx_03.fm.(1.2)
Instruction-Cache and Data-Cache Operation
March 27, 2006
Page 133 of 377
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