Inverter Function Block Inv - ABB RES670 Technical Manual

Section 15
Logic
15.7.3
15.7.3.1
15.7.3.2
15.7.3.3
15.7.4
434

Inverter function block INV

Function block
INV
INPUT OUT
IEC04000404_2_en.vsd
IEC04000404 V2 EN-US
Figure 160: INV function block
Signals
Table 261: INV Input signals
Name Type
INPUT BOOLEAN
Table 262: INV Output signals
Name Type
OUT BOOLEAN
Technical data
Table 263: Number of INV instances
Logic block
3 ms
INV 90
Loop delay function block LLD
The Logic loop delay function block (LLD) function is used to delay the output signal
one execution cycle, that is, the cycle time of the function blocks used.
Default Description
0 Input
Description
Output
Quantity with cycle time
8 ms
90
Phasor measurement unit RES670 2.2 ANSI
1MRK 511 408-UUS A
IP11011-1 v2
M11445-3 v1
PID-3803-INPUTSIGNALS v5
PID-3803-OUTPUTSIGNALS v4
GUID-0EC4192A-EF03-47C0-AEC1-09B68B411A98 v2
100 ms
240
GUID-05D959B5-A55B-437C-8E8F-831A4A357E24 v2
GUID-64B24094-010D-4B8F-8B7B-DDD49499AAE5 v3
Technical manual