Overview; Features - Samsung S3C2500B User Manual

S3C2500B
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16.1 OVERVIEW

The S3C2500B interrupt controller has a total of 39 interrupt sources. Interrupt requests can be generated by
internal function blocks or external pins.
The ARM940T core recognizes two kinds of interrupts: a normal interrupt request (IRQ) and a fast interrupt
request (FIQ). Therefore all S3C2500B interrupts can be categorized as either IRQ or FIQ. The S3C2500B
interrupt controller is level sensitive to each interrupt source.
Three special registers are used to control interrupt generation and handling:
— Interrupt priority registers (INTPRIORn): The index number of each interrupt source is written to the pre-
defined interrupt priority register field to obtain that priority. The interrupt priorities are pre-defined from 0x0
to 0x26.
— Interrupt mode register (INTMOD, EXTMOD): Defines the interrupt mode, IRQ or FIQ, for each interrupt
source.
— Interrupt mask register (INTMASK, EXTMASK): Indicates that the current interrupt has been disabled if the
corresponding mask bit is "1". If an interrupt mask bit is "0" the interrupt will be serviced normally. If the
global mask bit (bit 31) of EXTMASK register is set to "1", no interrupt is serviced. When the global mask bit
has been set to "0", the interrupt is serviced.

16.2 FEATURES

•
Supports IRQ and FIQ Interrupt Request
•
Level Sensitive Interrupt Sources
•
Supports 33 Internal Interrupt Sources
•
Supports 6 External Interrupt Sources
•
Supports Interrupt Sources Programmable to Different Priorities
•
Supports Global Interrupt Masking
INTERRUPT CONTROLLER
INTERRUPT CONTROLLER
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