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S3C2500B
Bit Number
Bit Name
[20]
Out mode,
Fifo FLUSH
(OFFLUSH)
[21]
Out mode,
SenD STALL
(OSDSTALL)
[22]
Out mode,
SenT STALL
(OSTSTALL)
[23]
Out mode,
CLear data TOGgle
(OCLTOG)
[24]
In mode, IN packet
ReaDY (IINRDY)
[25]
In mode, fifo Not
EMPty (INEMP)
Table 10-18. USBEP1CSR Register Description (Continued)
MCU
R/W
R/W
R/C
R
R/S
R
USB
C
This bit is valid only when endpoint 1 is set to OUT.
The MCU writes a "1" to flush the FIFO.
This bit can be set only when OORDY is set. The
packet due to be unloaded by the MCU will be
flushed.
R
This bit is valid only when endpoint 1 is set to OUT.
The MCU writes a "1" to this bit to issue a STALL
handshake to the USB.
The MCU clears this bit to end the STALL condition
S
This bit is valid only when endpoint 1 is set to OUT.
The USB sets this bit when an OUT token is ended
with a STALL handshake.
The USB issues a stall handshake to the host if it
sends more than MAXP data for the OUT token.
S
This bit is valid only when endpoint 1 is set to OUT.
When the MCU writes a "1" to this bit, the data
toggle sequence bit is reset to DATA0.
C
This bit is valid only when endpoint 1 is set to IN.
The MCU sets this bit, after writing a packet of data
into the FIFO. The USB clears this bit once the
packet has been successfully sent to the host. An
interrupt is generated when the USB clears this bit,
so the MCU can load the next packet, While this bit
is set , the MCU will not be able to write to the
FIFO.
If the SEND STALL bit is set by the MCU, this bit
can not be set.
S
This bit is valid only when endpoint 1 is set to IN.
Indicate there is at least one packet of data in FIFO.
if USBEP1CSR[25:24] is
10 = 1 packet IN FIFO
11 = 2 packets of MAXP =< 1/2 FIFO or
1 packet of MAXP > FIFO size
USB CONTROLLER
Description
10-27
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