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S3C2500B
Bit
Bit Name
Number
[7]
DMA Rx enable
(DRxEN)
[8]
DPLL enable (DPLLEN)
[9]
BRG enable (BRGEN)
[10]
Tx 4 word mode
(Tx4WD)
[11]
Rx 4 word mode
(Rx4WD)
Table 8-10. HCON Register Description (Continued)
The DRxEN bit lets the HDLC Rx operate on a bus system in DMA mode.
When DMA Rx is enabled, an interrupt request caused by the RxFA
status is inhibited, and the HDLC does not use the interrupt request to
request a data transfer. DMA Rx monitors the HRXFIFO and moves the
data from the HRXFIFO to memory. This bit is automatically disabled
when the next buffer descriptor pointer becomes null, or the owner bit is
not in DMA mode when the DTxSTSK bit is set.
Setting this bit enables the DPLL, causing the DPLL to enter search
mode. In Search mode, the DPLL searches for a locking edge in the
incoming data stream.
After DPLL is enabled (in NRZI mode for example), the DPLL starts
sampling immediately after the first edge is detected. (In FM mode, the
DPLL examines the clock edge of every other bit to decide what
correction must be made to remain in sync.) If the DPLL does not detect
an edge during the expected window, it sets the one clock missing bit.
If the DPLL does not detect an edge after two successive attempts, it sets
the two clock missing bit and the DPLL automatically enters the Search
mode. To reset both clocks missing latches, you can disable and re-
enable the DPLL using the reset Rx status.
This bit controls the operation of the baud rate generator (BRG). To
enable the BRG counter, set the BRGEN bit to '1'. To inhibit counting,
clear the bit to '0'.
When this bit is '0', and TxFA bit in status register is '1', it is indicated that
Tx FIFO is empty for 1 word. It means that 1-word data can be loaded to
Tx FIFO.
Similarly, when this bit is '1', the same status register bit indicate that 4
words of data can be loaded to Tx FIFO without reading the status bit for
a second time.
Specifically, the status register bit affected by the 1-word or 4-word
transfer setting are the transmit data available (TxFA) bit.
When this bit is '0', and the RxFA bit in the status register is '1', it is
indicated that Rx FIFO has 1-word data. It means that 1 word data can be
moved to memory.
Similarly, when this bit is '1', the same status register bit indicates that 4
words of data can be moved in the memory without reading the status bit
for a second time.
Specifically, the status register bit affected by the 1-word or 4-word
transfer setting are the receive data available (RxFA) bit, and the residue
bytes status bits, RxRB[3:0].
Description
HDLC CONTROLLER
8-31
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