Samsung S3C2500B User Manual page 331

S3C2500B
7.4.1.9 BDMA/MAC Receive Interrupt Enable Register
Registers Address
BMRXINTENA 0xF00A001C
BMRXINTENB 0xF00C001C
Table 7-21. BDMA/MAC Receive Interrupt Enable Register Description
Bit Number
[0] Enable MAC Rx missed roll
(MissRollIE)
[1] Enable MAC Rx alignment
(AlignErrIE)
[2] Enable MAC Rx CRC error
(CRCErrIE)
[3] Enable MAC Rx overflow
(OverflowIE)
[4] Enable MAC Rx long error
(LongErrIE)
[5] Enable MAC Rx receive parity
(RxParErrIE)
[6]
[15:7] Reserved
[16] Enable BDMA Rx done for
every received frames
(BRxDoneIE)
[17] Enable BDMA Rx not owner
interrupt (BRxNOIE)
[18] Enable BDMA Rx maximum
size over interrupt
(BRxMSOIE)
[19] Enable BDMA Rx
buffer(BRxBUFF) Overflow
Interrupt(BRxFullIE)
[20] Enable BDMA Rx early
notification interrupt
(BRxEarlyIE)
[31:21] Reserved
Table 7-20. BMRXINTEN Register
R/W
R/W
R/W
Bit Name
This bit enables MissRoll interrupt.
This bit enables AlignErr interrupt
This bit enables CRCErr interrupt.
This bit enables Overflow interrupt.
This bit enables LongErr interrupt.
This bit enables RxParErr interrupt.
– Factorial test bit
Not applicable.
This bit enables BRxDone interrupt.
This bit enables BRxNO interrupt.
This bit enables BRxMSO interrupt.
This bit enables BRxFull interrupt.
This bit enables BRxEarly interrupt.
Not applicable.
Description
BDMA/MAC Rx Interrupt Enable Register
BDMA/MAC Rx Interrupt Enable Register
ETHERNET CONTROLLER
Description
Reset Value
0x00000000
0x00000000
7-21