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SERIAL I/O (HIGH-SPEED UART)
31
30 29 28 27 26 25
R
E
S
H
T
C
F
F
S
H
E
E
R
O
N
N
T
R
14-8
24
23 22
21
20 19
R
D
R
T
R
T
T
F
F
F
S
R
T
T
R
L
L
S
T
[16] Transmit FIFO Enable (TFEN)
0 = Disable Transmit FIFO
1 = Enable Transmit FIFO
[17] Receive FIFO Enable (RFEN)
0 = Disable Receive FIFO
1 = Enable Receive FIFO
[18] Tranmit FIFO Reset (TFRST)
0 = Normal operation
1 = Reset Transmit FIFO
[19] Receive FIFO Reset (RFRST)
0 = Normal operation
[21:20] Transmit FIFO Trigger Level (TFTL)
00 = 30/32 byte data
01 = 24/32 byte data
10 = 16/32 byte data
11 = 8/32 byte data (empty Tx data / TxFIFO depth)
[23:22] Receive FIFO Trigger Level (RFTL)
00 = 1/32 byte data
01 = 8/32 byte data
10 = 18/32 byte data
11 = 28/32 byte data (valid Rx data / RxFIFO depth)
[24] Data Terminal Ready to pin (DTR)
0 = UnDTR0/UnDTR1 goes high level
1 = UnDTR0/UnDTR1 goes low level
[25] Request To Send to pin (RTS)
0 = UnRTS0/UnRTS1 goes high level
1 = UnRTS0/UnRTS1 goes low level
[27:26] Reserved (This bit should be cleared)
[28] Hardware Flow Control Enable (HFEN)
0 = Disable Hardware Flow Control
1 = Enable Hardware Flow Control
[29] Software Flow Control Enable (SFEN)
0 = Disable Software Flow Control
1 = Enable Software Flow Control
[30] Echo Mode (ECHO)
0 = Normal
[31] RTS/RTR selection (RTS/RTR)
0 = RTS
Figure 14-2. High-Speed UART Control Register (Continued)
18 17 16
15 14
13 12 11
T
R
T
I
W
S
F
F
F
R
L
T
R
E
E
B
S
N
N
T
1 = Reset Receive FIFO
1 = ECHO mode
1 = RTR
10
8 7 6
5
4
3
P
L
A
S
S
R
M
O
U
C
B
M
D
O
B
S
R
O
P
D
E
D
B
L
E
S3C2500B
2
1
0
T
M
O
D
E
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